here are some opportunities to do things a bit better with the naming of things now that our hindsight is better.
Signed-off-by: Ben Widawsky <[email protected]> --- drivers/gpu/drm/i915/i915_irq.c | 72 +++++++++++----------- drivers/gpu/drm/i915/i915_reg.h | 100 +++++++++++++------------------ drivers/gpu/drm/i915/intel_ringbuffer.c | 11 ++-- 3 files changed, 84 insertions(+), 99 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index cc4a633..a13762a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -403,17 +403,17 @@ static void snb_gt_irq_handler(struct drm_device *dev, u32 gt_iir) { - if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | - GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) + if (gt_iir & (INTEL_RENDER_USER_INTERRUPT | + INTEL_RENDER_PIPECTL_NOTIFY_INTERRUPT)) notify_ring(dev, &dev_priv->ring[RCS]); - if (gt_iir & GEN6_BSD_USER_INTERRUPT) + if (gt_iir & INTEL_BSD_USER_INTERRUPT) notify_ring(dev, &dev_priv->ring[VCS]); - if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) + if (gt_iir & INTEL_BLT_USER_INTERRUPT) notify_ring(dev, &dev_priv->ring[BCS]); - if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | - GT_GEN6_BSD_CS_ERROR_INTERRUPT | - GT_RENDER_CS_ERROR_INTERRUPT)) { + if (gt_iir & (INTEL_BLT_CS_ERROR_INTERRUPT | + INTEL_BSD_CS_ERROR_INTERRUPT | + INTEL_RENDER_MASTER_ERROR_INTERRUPT)) { DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); i915_handle_error(dev, false); } @@ -642,9 +642,10 @@ static void ilk_gt_irq_handler(struct drm_device *dev, struct drm_i915_private *dev_priv, u32 gt_iir) { - if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) + if (gt_iir & (INTEL_RENDER_USER_INTERRUPT | + INTEL_RENDER_PIPECTL_NOTIFY_INTERRUPT)) notify_ring(dev, &dev_priv->ring[RCS]); - if (gt_iir & GT_BSD_USER_INTERRUPT) + if (gt_iir & ILK_BSD_USER_INTERRUPT) notify_ring(dev, &dev_priv->ring[VCS]); } @@ -1718,7 +1719,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) /* enable kind of interrupts always enabled */ u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; - u32 render_irqs; + u32 gt_irqs; u32 hotplug_mask; dev_priv->irq_mask = ~display_mask; @@ -1734,17 +1735,16 @@ static int ironlake_irq_postinstall(struct drm_device *dev) I915_WRITE(GTIIR, I915_READ(GTIIR)); I915_WRITE(GTIMR, dev_priv->gt_irq_mask); + gt_irqs = INTEL_RENDER_USER_INTERRUPT; + if (IS_GEN6(dev)) - render_irqs = - GT_USER_INTERRUPT | - GEN6_BSD_USER_INTERRUPT | - GEN6_BLITTER_USER_INTERRUPT; + gt_irqs |= INTEL_BLT_USER_INTERRUPT | + INTEL_BSD_USER_INTERRUPT; else - render_irqs = - GT_USER_INTERRUPT | - GT_PIPE_NOTIFY | - GT_BSD_USER_INTERRUPT; - I915_WRITE(GTIER, render_irqs); + gt_irqs |= INTEL_RENDER_PIPECTL_NOTIFY_INTERRUPT | + ILK_BSD_USER_INTERRUPT; + + I915_WRITE(GTIER, gt_irqs); POSTING_READ(GTIER); if (HAS_PCH_CPT(dev)) { @@ -1788,7 +1788,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) DE_PLANEC_FLIP_DONE_IVB | DE_PLANEB_FLIP_DONE_IVB | DE_PLANEA_FLIP_DONE_IVB; - u32 render_irqs; + u32 gt_irqs; u32 hotplug_mask; dev_priv->irq_mask = ~display_mask; @@ -1808,9 +1808,9 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) I915_WRITE(GTIIR, I915_READ(GTIIR)); I915_WRITE(GTIMR, dev_priv->gt_irq_mask); - render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | - GEN6_BLITTER_USER_INTERRUPT; - I915_WRITE(GTIER, render_irqs); + gt_irqs = INTEL_RENDER_USER_INTERRUPT | INTEL_BSD_USER_INTERRUPT | + INTEL_BLT_USER_INTERRUPT; + I915_WRITE(GTIER, gt_irqs); POSTING_READ(GTIER); hotplug_mask = (SDE_CRT_HOTPLUG_CPT | @@ -1832,7 +1832,7 @@ static int ivybridge_irq_postinstall(struct drm_device *dev) static int valleyview_irq_postinstall(struct drm_device *dev) { drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 render_irqs; + u32 gt_irqs; u32 enable_mask; u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); u16 msid; @@ -1863,23 +1863,23 @@ static int valleyview_irq_postinstall(struct drm_device *dev) I915_WRITE(VLV_IIR, 0xffffffff); I915_WRITE(VLV_IIR, 0xffffffff); - render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT | - GT_GEN6_BLT_CS_ERROR_INTERRUPT | - GT_GEN6_BLT_USER_INTERRUPT | - GT_GEN6_BSD_USER_INTERRUPT | - GT_GEN6_BSD_CS_ERROR_INTERRUPT | - GT_GEN7_L3_PARITY_ERROR_INTERRUPT | - GT_PIPE_NOTIFY | - GT_RENDER_CS_ERROR_INTERRUPT | - GT_SYNC_STATUS | - GT_USER_INTERRUPT; + gt_irqs = INTEL_BLT_FLUSHDW_NOTIFY_INTERRUPT | + INTEL_BLT_CS_ERROR_INTERRUPT | + INTEL_BLT_USER_INTERRUPT | + INTEL_BSD_USER_INTERRUPT | + INTEL_BSD_CS_ERROR_INTERRUPT | + INTEL_RENDER_L3_PARITY_ERROR_INTERRUPT | + INTEL_RENDER_PIPECTL_NOTIFY_INTERRUPT | + INTEL_RENDER_MASTER_ERROR_INTERRUPT | + INTEL_RENDER_SYNC_STATUS_INTERRUPT | + INTEL_RENDER_USER_INTERRUPT; - dev_priv->gt_irq_mask = ~render_irqs; + dev_priv->gt_irq_mask = ~gt_irqs; I915_WRITE(GTIIR, I915_READ(GTIIR)); I915_WRITE(GTIIR, I915_READ(GTIIR)); I915_WRITE(GTIMR, 0); - I915_WRITE(GTIER, render_irqs); + I915_WRITE(GTIER, gt_irqs); POSTING_READ(GTIER); /* ack & enable invalid PTE error interrupts */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 645d012..b54c54b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -526,24 +526,6 @@ #define VLV_IIR 0x1820a4 #define VLV_IMR 0x1820a8 #define VLV_ISR 0x1820ac -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) -#define I915_DISPLAY_PORT_INTERRUPT (1<<17) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ -#define I915_HWB_OOM_INTERRUPT (1<<13) -#define I915_SYNC_STATUS_INTERRUPT (1<<12) -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) -#define I915_DEBUG_INTERRUPT (1<<2) -#define I915_USER_INTERRUPT (1<<1) -#define I915_ASLE_INTERRUPT (1<<0) -#define I915_BSD_USER_INTERRUPT (1<<25) #define EIR 0x020b0 #define EMR 0x020b4 #define ESR 0x020b8 @@ -651,28 +633,6 @@ #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) -/* GEN6 interrupt control - * Note that the per-ring interrupt bits do alias with the global interrupt bits - * in GTIMR. */ -#define GEN6_RENDER_HWSTAM 0x2098 -#define GEN6_RENDER_IMR 0x20a8 -#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7) -#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6) -#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5) -#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4) -#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3) -#define GEN6_RENDER_SYNC_STATUS (1 << 2) -#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1) -#define GEN6_RENDER_USER_INTERRUPT (1 << 0) - -#define GEN6_BLITTER_HWSTAM 0x22098 -#define GEN6_BLITTER_IMR 0x220a8 -#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26) -#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25) -#define GEN6_BLITTER_SYNC_STATUS (1 << 24) -#define GEN6_BLITTER_USER_INTERRUPT (1 << 22) - #define GEN6_BLITTER_ECOSKPD 0x221d0 #define GEN6_BLITTER_LOCK_SHIFT 16 #define GEN6_BLITTER_FBC_NOTIFY (1<<3) @@ -683,9 +643,48 @@ #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0 #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3) -#define GEN6_BSD_HWSTAM 0x12098 -#define GEN6_BSD_IMR 0x120a8 -#define GEN6_BSD_USER_INTERRUPT (1 << 12) +/* On modern GEN architectures interrupt control consists of two sets + * of registers. The first set pertains to the ring generating the + * interrupt. The second control is for the functional block generating the + * interrupt. These are PM, GT, DE, etc. + * + * Luckily *knocks on wood* all the ring interrupt bits match up with the + * GT interrupt bits, so we don't need to duplicate the defines. + * + * These defines should cover us from ILK->HSW. VLV may have exceptions. + */ +#define INTEL_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) +#define INTEL_BLT_CS_ERROR_INTERRUPT (1 << 25) +#define INTEL_BLT_USER_INTERRUPT (1 << 22) +#define INTEL_BSD_CS_ERROR_INTERRUPT (1 << 15) +#define INTEL_BSD_USER_INTERRUPT (1 << 12) +#define ILK_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ +#define INTEL_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* ivb & hsw */ +#define INTEL_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) +#define INTEL_RENDER_MASTER_ERROR_INTERRUPT (1 << 3) +#define INTEL_RENDER_SYNC_STATUS_INTERRUPT (1 << 2) +#define INTEL_RENDER_DEBUG_INTERRUPT (1 << 1) +#define INTEL_RENDER_USER_INTERRUPT (1 << 0) + +/* These are all the "old" interrupts and should be relevant through i965 */ +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) +#define I915_DISPLAY_PORT_INTERRUPT (1<<17) +#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ +#define I915_HWB_OOM_INTERRUPT (1<<13) +#define I915_SYNC_STATUS_INTERRUPT (1<<12) +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) +#define I915_DEBUG_INTERRUPT (1<<2) +#define I915_USER_INTERRUPT (1<<1) +#define I915_ASLE_INTERRUPT (1<<0) +#define I915_BSD_USER_INTERRUPT (1 << 25) #define GEN6_BSD_RNCID 0x12198 @@ -3243,21 +3242,6 @@ #define DEIIR 0x44008 #define DEIER 0x4400c -/* GT interrupt. - * Note that for gen6+ the ring-specific interrupt bits do alias with the - * corresponding bits in the per-ring interrupt control registers. */ -#define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) -#define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) -#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) -#define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) -#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) -#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ -#define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) -#define GT_PIPE_NOTIFY (1 << 4) -#define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) -#define GT_SYNC_STATUS (1 << 2) -#define GT_USER_INTERRUPT (1 << 0) - #define GTISR 0x44010 #define GTIMR 0x44014 #define GTIIR 0x44018 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5b30815..7ce40c4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1327,7 +1327,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->flush = gen6_render_ring_flush; ring->irq_get = gen6_ring_get_irq; ring->irq_put = gen6_ring_put_irq; - ring->irq_enable_mask = GT_USER_INTERRUPT; + ring->irq_enable_mask = INTEL_RENDER_USER_INTERRUPT; ring->get_seqno = gen6_ring_get_seqno; ring->sync_to = gen6_ring_sync; ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID; @@ -1341,7 +1341,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev) ring->get_seqno = pc_render_get_seqno; ring->irq_get = gen5_ring_get_irq; ring->irq_put = gen5_ring_put_irq; - ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; + ring->irq_enable_mask = INTEL_RENDER_USER_INTERRUPT | + INTEL_RENDER_PIPECTL_NOTIFY_INTERRUPT; } else { ring->add_request = i9xx_add_request; if (INTEL_INFO(dev)->gen < 4) @@ -1460,7 +1461,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) ring->flush = gen6_bsd_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; - ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; + ring->irq_enable_mask = INTEL_BSD_USER_INTERRUPT; ring->irq_get = gen6_ring_get_irq; ring->irq_put = gen6_ring_put_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; @@ -1476,7 +1477,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) ring->add_request = i9xx_add_request; ring->get_seqno = ring_get_seqno; if (IS_GEN5(dev)) { - ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; + ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; ring->irq_get = gen5_ring_get_irq; ring->irq_put = gen5_ring_put_irq; } else { @@ -1505,7 +1506,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) ring->flush = gen6_ring_flush; ring->add_request = gen6_add_request; ring->get_seqno = gen6_ring_get_seqno; - ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; + ring->irq_enable_mask = INTEL_BLT_USER_INTERRUPT; ring->irq_get = gen6_ring_get_irq; ring->irq_put = gen6_ring_put_irq; ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; -- 1.7.10.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
