This is definitely needed to pass igt test on bxt
'gem_exec_suspend --run-subtest basic-S3'
Tested-by: Mika Kahola <mika.kah...@intel.com>
On Mon, 2017-01-09 at 14:46 +0530, Vidya Srinivas wrote:
> From: Uma Shankar <uma.shan...@intel.com>
>
> Enable MIPI IO WA for BXT DSI as per bspec.
>
> Signed-off-by: Uma Shankar <uma.shan...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_dsi.c | 9 +++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 71b978a..b9d7e98 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8301,6 +8301,9 @@ enum {
> #define _BXT_MIPIC_PORT_CTRL 0x6B8C0
> #define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc,
> _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
>
> +#define BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR _MMIO(0
> x138090)
> +#define MIPIO_RST_CTRL (1 <<
> 2)
> +
> #define DPI_ENABLE (1 << 31)
> /* A + C */
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
> #define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index a4bda92..9252490 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -366,6 +366,11 @@ static void bxt_dsi_device_ready(struct
> intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> + /* Add MIPI IO reset programming for modeset */
> + val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> + I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> + val | MIPIO_RST_CTRL);
> +
Should we move this WA to intel_dsi_pre_enable() as the counterpart of
this WA is defined intel_dsi_post_disable()?
> /* Enable MIPI PHY transparent latch */
> for_each_dsi_port(port, intel_dsi->ports) {
> val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> @@ -757,6 +762,10 @@ static void intel_dsi_post_disable(struct
> intel_encoder *encoder,
> drm_panel_power_off(intel_dsi->panel);
> msleep(intel_dsi->panel_off_delay);
>
> + val = I915_READ(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR);
> + I915_WRITE(BXT_P_CR_GT_DISP_PWRON_0_2_0_GTTMMADR,
> + val & ~MIPIO_RST_CTRL);
> +
> intel_disable_dsi_pll(encoder);
>
> /* Panel Disable over CRC PMIC */
--
Mika Kahola - Intel OTC
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