On Mon, 02 Jan 2017, Madhav Chauhan <[email protected]> wrote:
> From: Deepak M <[email protected]>
>
> Program the clk lane and tlpx time count registers
> to configure DSI PHY.
>
> v2: Addressed Jani's Review comments(renamed bit field macros)
> v3: Program clk lane timing reg same as dphy param reg.
>
> Signed-off-by: Deepak M <[email protected]>
> Signed-off-by: Madhav Chauhan <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> drivers/gpu/drm/i915/intel_dsi.c | 7 +++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00970aa..f111c3f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8554,6 +8554,14 @@ enum {
> #define LP_BYTECLK_SHIFT 0
> #define LP_BYTECLK_MASK (0xffff << 0)
>
> +#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base +
> 0xb0a4)
> +#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base +
> 0xb8a4)
> +#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port,
> _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
> +
> +#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base +
> 0xb098)
> +#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base +
> 0xb898)
> +#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port,
> _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
> +
> /* bits 31:0 */
> #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
> #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index 16732e7..be81283 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -1279,6 +1279,13 @@ static void intel_dsi_prepare(struct intel_encoder
> *intel_encoder,
> */
> I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
IIUC you also need to write 1 to MIPI_LP_BYTECLK(port) on GLK. Or how do
you read the spec on the register?
>
> + if (IS_GEMINILAKE(dev_priv)) {
> + I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
> + intel_dsi->lp_byte_clk);
> + /* Shadow of DPHY reg */
> + I915_WRITE(MIPI_CLK_LANE_TIMING(port),
> intel_dsi->dphy_reg);
The spec lists only specific valid values for the register. Is the spec
right?
BR,
Jani.
> + }
> +
> /* the bw essential for transmitting 16 long packets containing
> * 252 bytes meant for dcs write memory command is programmed in
> * this register in terms of byte clocks. based on dsi transfer
--
Jani Nikula, Intel Open Source Technology Center
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