HuC firmware is mapped at GuC accessible range. Let's add an assert to verify that.
v2: Split from previous commit (Michał) v3: Oops, hit send before compiling, s/huc_fw/huc->fw Cc: Anusha Srivatsa <[email protected]> Cc: Arkadiusz Hiler <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Michal Wajdeczko <[email protected]> Signed-off-by: Michał Winiarski <[email protected]> --- drivers/gpu/drm/i915/intel_huc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index d1e65fa..c144609 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -299,7 +299,7 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv) int ret; u32 data[2]; - if (huc_fw->load_status != INTEL_UC_FIRMWARE_SUCCESS) + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) return; vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0, @@ -312,7 +312,7 @@ void intel_guc_auth_huc(struct drm_i915_private *dev_priv) /* Specify auth action and where public signature is. */ data[0] = INTEL_GUC_ACTION_AUTHENTICATE_HUC; - data[1] = i915_ggtt_offset(vma) + huc->fw.rsa_offset; + data[1] = guc_ggtt_offset(vma) + huc->fw.rsa_offset; ret = intel_guc_send(guc, data, ARRAY_SIZE(data)); if (ret) { -- 2.9.3 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
