On Fri, Jan 20, 2017 at 08:21:52PM +0200, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > Rather than recomptuing the pipe pixel rate on demand everwhere, let's
recomputing, everywhere > just stick the precomputed value into the crtc state. > > v2: Rebase due to min_pixclk[] code movement > Document the new pixel_rate struct member (Ander) > Combine vlv/chv with bdw+ in intel_modeset_readout_hw_state() > > Cc: Ander Conselvan De Oliveira <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 36 > ++++++++++++++++++++++++++++-------- > drivers/gpu/drm/i915/intel_drv.h | 6 ++++++ > drivers/gpu/drm/i915/intel_fbc.c | 3 +-- > drivers/gpu/drm/i915/intel_pm.c | 14 +++++++------- > 4 files changed, 42 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 0f4272f98648..a825107b362b 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -7165,7 +7165,7 @@ static bool pipe_config_supports_ips(struct > drm_i915_private *dev_priv, > * > * Should measure whether using a lower cdclk w/o IPS > */ > - return ilk_pipe_pixel_rate(pipe_config) <= > + return pipe_config->pixel_rate <= > dev_priv->max_cdclk_freq * 95 / 100; > } > > @@ -7189,6 +7189,19 @@ static bool intel_crtc_supports_double_wide(const > struct intel_crtc *crtc) > (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); > } > > +static void intel_crtc_compute_pixel_rate(struct intel_crtc_state > *crtc_state) > +{ > + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); > + > + if (HAS_GMCH_DISPLAY(dev_priv)) > + /* FIXME calculate proper pipe pixel rate for GMCH pfit */ > + crtc_state->pixel_rate = > + crtc_state->base.adjusted_mode.crtc_clock; > + else > + crtc_state->pixel_rate = > + ilk_pipe_pixel_rate(crtc_state); > +} > + > static int intel_crtc_compute_config(struct intel_crtc *crtc, > struct intel_crtc_state *pipe_config) > { > @@ -7235,6 +7248,8 @@ static int intel_crtc_compute_config(struct intel_crtc > *crtc, > adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) > return -EINVAL; > > + intel_crtc_compute_pixel_rate(pipe_config); > + > if (HAS_IPS(dev_priv)) > hsw_compute_ips_config(crtc, pipe_config); > > @@ -10283,7 +10298,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state > *state) > continue; > } > > - pixel_rate = ilk_pipe_pixel_rate(crtc_state); > + pixel_rate = crtc_state->pixel_rate; > > if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) > pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, > @@ -12792,9 +12807,10 @@ static void intel_dump_pipe_config(struct intel_crtc > *crtc, > DRM_DEBUG_KMS("adjusted mode:\n"); > drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); > intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); > - DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d\n", > + DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", > pipe_config->port_clock, > - pipe_config->pipe_src_w, pipe_config->pipe_src_h); > + pipe_config->pipe_src_w, pipe_config->pipe_src_h, > + pipe_config->pixel_rate); > > if (INTEL_GEN(dev_priv) >= 9) > DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: > %d\n", > @@ -13367,6 +13383,7 @@ intel_pipe_config_compare(struct drm_i915_private > *dev_priv, > } > > PIPE_CONF_CHECK_I(scaler_state.scaler_id); > + PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); > } > > /* BDW+ don't expose a synchronous way to read the state */ > @@ -13658,6 +13675,8 @@ verify_crtc_state(struct drm_crtc *crtc, > } > } > > + intel_crtc_compute_pixel_rate(pipe_config); > + > if (!new_crtc_state->active) > return; > > @@ -17102,10 +17121,11 @@ static void intel_modeset_readout_hw_state(struct > drm_device *dev) > */ > crtc_state->base.mode.private_flags = > I915_MODE_FLAG_INHERITED; > > - if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) > - pixclk = ilk_pipe_pixel_rate(crtc_state); > - else if (IS_VALLEYVIEW(dev_priv) || > IS_CHERRYVIEW(dev_priv)) > - pixclk = > crtc_state->base.adjusted_mode.crtc_clock; > + intel_crtc_compute_pixel_rate(crtc_state); > + > + if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) > || > + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + pixclk = crtc_state->pixel_rate; > else > WARN_ON(dev_priv->display.modeset_calc_cdclk); > > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 0cec0013ace0..3b263d15e16e 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -542,6 +542,12 @@ struct intel_crtc_state { > * and get clipped at the edges. */ > int pipe_src_w, pipe_src_h; > > + /* > + * Pipe pixel rate, adjusted for > + * panel fitter/pipe scaler downscaling. > + */ > + unsigned int pixel_rate; > + > /* Whether to set up the PCH/FDI. Note that we never allow sharing > * between pch encoders and cpu encoders. */ > bool has_pch_encoder; > diff --git a/drivers/gpu/drm/i915/intel_fbc.c > b/drivers/gpu/drm/i915/intel_fbc.c > index 89fe5c8464df..2b4c176510d4 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -743,8 +743,7 @@ static void intel_fbc_update_state_cache(struct > intel_crtc *crtc, > > cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags; > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > - cache->crtc.hsw_bdw_pixel_rate = > - ilk_pipe_pixel_rate(crtc_state); > + cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; > > cache->plane.rotation = plane_state->base.rotation; > cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 249623d45be0..94819435641c 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1807,12 +1807,12 @@ static uint32_t ilk_compute_pri_wm(const struct > intel_crtc_state *cstate, > > cpp = pstate->base.fb->format->cpp[0]; > > - method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value); > + method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); > > if (!is_lp) > return method1; > > - method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), > + method2 = ilk_wm_method2(cstate->pixel_rate, > cstate->base.adjusted_mode.crtc_htotal, > drm_rect_width(&pstate->base.dst), > cpp, mem_value); > @@ -1836,8 +1836,8 @@ static uint32_t ilk_compute_spr_wm(const struct > intel_crtc_state *cstate, > > cpp = pstate->base.fb->format->cpp[0]; > > - method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value); > - method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), > + method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); > + method2 = ilk_wm_method2(cstate->pixel_rate, > cstate->base.adjusted_mode.crtc_htotal, > drm_rect_width(&pstate->base.dst), > cpp, mem_value); > @@ -1863,7 +1863,7 @@ static uint32_t ilk_compute_cur_wm(const struct > intel_crtc_state *cstate, > if (!cstate->base.active) > return 0; > > - return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), > + return ilk_wm_method2(cstate->pixel_rate, > cstate->base.adjusted_mode.crtc_htotal, > width, cpp, mem_value); > } > @@ -3547,7 +3547,7 @@ static uint32_t skl_adjusted_plane_pixel_rate(const > struct intel_crtc_state *cst > * Adjusted plane pixel rate is just the pipe's adjusted pixel rate > * with additional adjustments for plane-specific scaling. > */ > - adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate); > + adjusted_pixel_rate = cstate->pixel_rate; > downscale_amount = skl_plane_downscale_amount(pstate); > > pixel_rate = adjusted_pixel_rate * downscale_amount >> 16; > @@ -3775,7 +3775,7 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate) > if (!cstate->base.active) > return 0; > > - pixel_rate = ilk_pipe_pixel_rate(cstate); > + pixel_rate = cstate->pixel_rate; > > if (WARN_ON(pixel_rate == 0)) > return 0; > -- > 2.10.2 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
