On Mon, 4 Jun 2012 18:39:19 +0200 Daniel Vetter <[email protected]> wrote:
> ... instead of abusing mode->clock by storing it in there - we > shouldn't touch that one at all. This patch is the first prep step to > constify the mode argument of the intel_dp_mode_fixup function. > > The next patch will stop us from modifying mode->clock. > > Signed-Off-by: Daniel Vetter <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 16 ++++++++-------- > drivers/gpu/drm/i915/intel_dp.c | 12 ++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 3 files changed, 22 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 9f5148ac..0161d94 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4416,16 +4416,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc > *crtc, > /* CPU eDP doesn't require FDI link, so just set DP M/N > according to current link config */ > if (is_cpu_edp) { > - target_clock = mode->clock; > intel_edp_link_config(edp_encoder, &lane, &link_bw); > } else { > - /* [e]DP over FDI requires target mode clock > - instead of link clock */ > - if (is_dp) > - target_clock = mode->clock; > - else > - target_clock = adjusted_mode->clock; > - > /* FDI is a binary signal running at ~2.7GHz, encoding > * each output octet as 10 bits. The actual frequency > * is stored as a divider into a 100MHz clock, and the > @@ -4436,6 +4428,14 @@ static int ironlake_crtc_mode_set(struct drm_crtc > *crtc, > link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; > } > > + /* [e]DP over FDI requires target mode clock instead of link clock. */ > + if (edp_encoder) > + target_clock = intel_edp_target_clock(edp_encoder, mode); > + else if (is_dp) > + target_clock = mode->clock; > + else > + target_clock = adjusted_mode->clock; > + > /* determine panel color depth */ > temp = I915_READ(PIPECONF(pipe)); > temp &= ~PIPE_BPC_MASK; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index ade98e0..ae7c623 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -152,6 +152,18 @@ intel_edp_link_config(struct intel_encoder > *intel_encoder, > *link_bw = 270000; > } > > +int > +intel_edp_target_clock(struct intel_encoder *intel_encoder, > + struct drm_display_mode *mode) > +{ > + struct intel_dp *intel_dp = container_of(intel_encoder, struct > intel_dp, base); > + > + if (intel_dp->panel_fixed_mode) > + return intel_dp->panel_fixed_mode->clock; > + else > + return mode->clock; > +} > + > static int > intel_dp_max_lane_count(struct intel_dp *intel_dp) > { > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 39d7b07..6a2ae30 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -359,6 +359,8 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct > drm_display_mode *mode, > struct drm_display_mode *adjusted_mode); > extern bool intel_dpd_is_edp(struct drm_device *dev); > extern void intel_edp_link_config(struct intel_encoder *, int *, int *); > +extern int intel_edp_target_clock(struct intel_encoder *, > + struct drm_display_mode *mode); > extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); > extern int intel_plane_init(struct drm_device *dev, enum pipe pipe); > extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, Yeah looks good, we'll need testing though. This patch could change the clock rate used on PCH attached eDP panels. Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
