Chris Wilson <[email protected]> writes: > Make checkpatch happy and make the use of u32/u64 consistent throughout > i915_gem_gtt.[ch] > > Signed-off-by: Chris Wilson <[email protected]>
Now it looks pretty. Reviewed-by: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 83 > +++++++++++++++++++------------------ > drivers/gpu/drm/i915/i915_gem_gtt.h | 56 ++++++++++++------------- > 2 files changed, 69 insertions(+), 70 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 9dd161a4a8a2..65892d6e3877 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -887,7 +887,7 @@ static void gen8_ppgtt_insert_3lvl(struct > i915_address_space *vm, > > static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, > struct sg_table *pages, > - uint64_t start, > + u64 start, > enum i915_cache_level cache_level, > u32 unused) > { > @@ -1161,25 +1161,25 @@ static int gen8_ppgtt_alloc_4lvl(struct > i915_address_space *vm, > > static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt, > struct i915_page_directory_pointer *pdp, > - uint64_t start, uint64_t length, > + u64 start, u64 length, > gen8_pte_t scratch_pte, > struct seq_file *m) > { > struct i915_page_directory *pd; > - uint32_t pdpe; > + u32 pdpe; > > gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { > struct i915_page_table *pt; > - uint64_t pd_len = length; > - uint64_t pd_start = start; > - uint32_t pde; > + u64 pd_len = length; > + u64 pd_start = start; > + u32 pde; > > if (pdp->page_directory[pdpe] == ppgtt->base.scratch_pd) > continue; > > seq_printf(m, "\tPDPE #%d\n", pdpe); > gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { > - uint32_t pte; > + u32 pte; > gen8_pte_t *pt_vaddr; > > if (pd->page_table[pde] == ppgtt->base.scratch_pt) > @@ -1187,10 +1187,9 @@ static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt, > > pt_vaddr = kmap_atomic_px(pt); > for (pte = 0; pte < GEN8_PTES; pte += 4) { > - uint64_t va = > - (pdpe << GEN8_PDPE_SHIFT) | > - (pde << GEN8_PDE_SHIFT) | > - (pte << GEN8_PTE_SHIFT); > + u64 va = (pdpe << GEN8_PDPE_SHIFT | > + pde << GEN8_PDE_SHIFT | > + pte << GEN8_PTE_SHIFT); > int i; > bool found = false; > > @@ -1224,7 +1223,7 @@ static void gen8_dump_ppgtt(struct i915_hw_ppgtt > *ppgtt, struct seq_file *m) > if (!USES_FULL_48BIT_PPGTT(vm->i915)) { > gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, > m); > } else { > - uint64_t pml4e; > + u64 pml4e; > struct i915_pml4 *pml4 = &ppgtt->pml4; > struct i915_page_directory_pointer *pdp; > > @@ -1406,7 +1405,7 @@ static inline void gen6_write_pde(const struct > i915_hw_ppgtt *ppgtt, > /* Write all the page tables found in the ppgtt structure to incrementing > page > * directories. */ > static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt, > - uint32_t start, uint32_t length) > + u32 start, u32 length) > { > struct i915_page_table *pt; > unsigned int pde; > @@ -1418,7 +1417,7 @@ static void gen6_write_page_range(struct i915_hw_ppgtt > *ppgtt, > wmb(); > } > > -static inline uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) > +static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt) > { > GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); > return ppgtt->pd.base.ggtt_offset << 10; > @@ -1512,7 +1511,7 @@ static void gen8_ppgtt_enable(struct drm_i915_private > *dev_priv) > static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) > { > struct intel_engine_cs *engine; > - uint32_t ecochk, ecobits; > + u32 ecochk, ecobits; > enum intel_engine_id id; > > ecobits = I915_READ(GAC_ECO_BITS); > @@ -1536,7 +1535,7 @@ static void gen7_ppgtt_enable(struct drm_i915_private > *dev_priv) > > static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) > { > - uint32_t ecochk, gab_ctl, ecobits; > + u32 ecochk, gab_ctl, ecobits; > > ecobits = I915_READ(GAC_ECO_BITS); > I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | > @@ -1588,8 +1587,9 @@ static void gen6_ppgtt_clear_range(struct > i915_address_space *vm, > > static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, > struct sg_table *pages, > - uint64_t start, > - enum i915_cache_level cache_level, u32 > flags) > + u64 start, > + enum i915_cache_level cache_level, > + u32 flags) > { > struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); > unsigned first_entry = start >> PAGE_SHIFT; > @@ -1689,7 +1689,7 @@ static void gen6_ppgtt_cleanup(struct > i915_address_space *vm) > struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); > struct i915_page_directory *pd = &ppgtt->pd; > struct i915_page_table *pt; > - uint32_t pde; > + u32 pde; > > drm_mm_remove_node(&ppgtt->node); > > @@ -1747,10 +1747,10 @@ static int gen6_ppgtt_alloc(struct i915_hw_ppgtt > *ppgtt) > } > > static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, > - uint64_t start, uint64_t length) > + u64 start, u64 length) > { > struct i915_page_table *unused; > - uint32_t pde; > + u32 pde; > > gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) > ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; > @@ -2044,7 +2044,7 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t > pte) > > static void gen8_ggtt_insert_page(struct i915_address_space *vm, > dma_addr_t addr, > - uint64_t offset, > + u64 offset, > enum i915_cache_level level, > u32 unused) > { > @@ -2059,8 +2059,9 @@ static void gen8_ggtt_insert_page(struct > i915_address_space *vm, > > static void gen8_ggtt_insert_entries(struct i915_address_space *vm, > struct sg_table *st, > - uint64_t start, > - enum i915_cache_level level, u32 unused) > + u64 start, > + enum i915_cache_level level, > + u32 unused) > { > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > struct sgt_iter sgt_iter; > @@ -2085,7 +2086,7 @@ static void gen8_ggtt_insert_entries(struct > i915_address_space *vm, > struct insert_entries { > struct i915_address_space *vm; > struct sg_table *st; > - uint64_t start; > + u64 start; > enum i915_cache_level level; > u32 flags; > }; > @@ -2100,7 +2101,7 @@ static int gen8_ggtt_insert_entries__cb(void *_arg) > > static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, > struct sg_table *st, > - uint64_t start, > + u64 start, > enum i915_cache_level level, > u32 flags) > { > @@ -2110,7 +2111,7 @@ static void gen8_ggtt_insert_entries__BKL(struct > i915_address_space *vm, > > static void gen6_ggtt_insert_page(struct i915_address_space *vm, > dma_addr_t addr, > - uint64_t offset, > + u64 offset, > enum i915_cache_level level, > u32 flags) > { > @@ -2131,8 +2132,9 @@ static void gen6_ggtt_insert_page(struct > i915_address_space *vm, > */ > static void gen6_ggtt_insert_entries(struct i915_address_space *vm, > struct sg_table *st, > - uint64_t start, > - enum i915_cache_level level, u32 flags) > + u64 start, > + enum i915_cache_level level, > + u32 flags) > { > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm; > @@ -2151,12 +2153,12 @@ static void gen6_ggtt_insert_entries(struct > i915_address_space *vm, > } > > static void nop_clear_range(struct i915_address_space *vm, > - uint64_t start, uint64_t length) > + u64 start, u64 length) > { > } > > static void gen8_ggtt_clear_range(struct i915_address_space *vm, > - uint64_t start, uint64_t length) > + u64 start, u64 length) > { > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > unsigned first_entry = start >> PAGE_SHIFT; > @@ -2178,8 +2180,7 @@ static void gen8_ggtt_clear_range(struct > i915_address_space *vm, > } > > static void gen6_ggtt_clear_range(struct i915_address_space *vm, > - uint64_t start, > - uint64_t length) > + u64 start, u64 length) > { > struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); > unsigned first_entry = start >> PAGE_SHIFT; > @@ -2203,7 +2204,7 @@ static void gen6_ggtt_clear_range(struct > i915_address_space *vm, > > static void i915_ggtt_insert_page(struct i915_address_space *vm, > dma_addr_t addr, > - uint64_t offset, > + u64 offset, > enum i915_cache_level cache_level, > u32 unused) > { > @@ -2215,8 +2216,9 @@ static void i915_ggtt_insert_page(struct > i915_address_space *vm, > > static void i915_ggtt_insert_entries(struct i915_address_space *vm, > struct sg_table *pages, > - uint64_t start, > - enum i915_cache_level cache_level, u32 > unused) > + u64 start, > + enum i915_cache_level cache_level, > + u32 unused) > { > unsigned int flags = (cache_level == I915_CACHE_NONE) ? > AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; > @@ -2225,8 +2227,7 @@ static void i915_ggtt_insert_entries(struct > i915_address_space *vm, > } > > static void i915_ggtt_clear_range(struct i915_address_space *vm, > - uint64_t start, > - uint64_t length) > + u64 start, u64 length) > { > intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); > } > @@ -2635,7 +2636,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, > u64 size) > * writing this data shouldn't be harmful even in those cases. */ > static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) > { > - uint64_t pat; > + u64 pat; > > pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal > objects, no eLLC */ > GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something > pointing to ptes? */ > @@ -2670,7 +2671,7 @@ static void bdw_setup_private_ppat(struct > drm_i915_private *dev_priv) > > static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) > { > - uint64_t pat; > + u64 pat; > > /* > * Map WB on BDW to snooped on CHV. > @@ -3067,7 +3068,7 @@ static noinline struct sg_table * > intel_rotate_pages(struct intel_rotation_info *rot_info, > struct drm_i915_gem_object *obj) > { > - const size_t n_pages = obj->base.size / PAGE_SIZE; > + const unsigned long n_pages = obj->base.size / PAGE_SIZE; > unsigned int size = intel_rotation_info_size(rot_info); > struct sgt_iter sgt_iter; > dma_addr_t dma_addr; > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h > b/drivers/gpu/drm/i915/i915_gem_gtt.h > index e85ff6c97208..f7d4e194a227 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -53,11 +53,11 @@ > struct drm_i915_file_private; > struct drm_i915_fence_reg; > > -typedef uint32_t gen6_pte_t; > -typedef uint64_t gen8_pte_t; > -typedef uint64_t gen8_pde_t; > -typedef uint64_t gen8_ppgtt_pdpe_t; > -typedef uint64_t gen8_ppgtt_pml4e_t; > +typedef u32 gen6_pte_t; > +typedef u64 gen8_pte_t; > +typedef u64 gen8_pde_t; > +typedef u64 gen8_ppgtt_pdpe_t; > +typedef u64 gen8_ppgtt_pml4e_t; > > #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) > > @@ -143,7 +143,7 @@ typedef uint64_t gen8_ppgtt_pml4e_t; > #define GEN8_PPAT_WC (1<<0) > #define GEN8_PPAT_UC (0<<0) > #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) > -#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) > +#define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) > > struct sg_table; > > @@ -210,7 +210,7 @@ struct i915_page_dma { > /* For gen6/gen7 only. This is the offset in the GGTT > * where the page directory entries for PPGTT begin > */ > - uint32_t ggtt_offset; > + u32 ggtt_offset; > }; > }; > > @@ -305,20 +305,19 @@ struct i915_address_space { > /* flags for pte_encode */ > #define PTE_READ_ONLY (1<<0) > int (*allocate_va_range)(struct i915_address_space *vm, > - uint64_t start, > - uint64_t length); > + u64 start, u64 length); > void (*clear_range)(struct i915_address_space *vm, > - uint64_t start, > - uint64_t length); > + u64 start, u64 length); > void (*insert_page)(struct i915_address_space *vm, > dma_addr_t addr, > - uint64_t offset, > + u64 offset, > enum i915_cache_level cache_level, > u32 flags); > void (*insert_entries)(struct i915_address_space *vm, > struct sg_table *st, > - uint64_t start, > - enum i915_cache_level cache_level, u32 flags); > + u64 start, > + enum i915_cache_level cache_level, > + u32 flags); > void (*cleanup)(struct i915_address_space *vm); > /** Unmap an object from an address space. This usually consists of > * setting the valid PTE entries to a reserved scratch page. */ > @@ -411,9 +410,9 @@ struct i915_hw_ppgtt { > (pt = (pd)->page_table[iter], true); \ > ++iter) > > -static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) > +static inline u32 i915_pte_index(u64 address, unsigned int pde_shift) > { > - const uint32_t mask = NUM_PTE(pde_shift) - 1; > + const u32 mask = NUM_PTE(pde_shift) - 1; > > return (address >> PAGE_SHIFT) & mask; > } > @@ -422,11 +421,10 @@ static inline uint32_t i915_pte_index(uint64_t address, > uint32_t pde_shift) > * does not cross a page table boundary, so the max value would be > * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. > */ > -static inline uint32_t i915_pte_count(uint64_t addr, size_t length, > - uint32_t pde_shift) > +static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int > pde_shift) > { > - const uint64_t mask = ~((1ULL << pde_shift) - 1); > - uint64_t end; > + const u64 mask = ~((1ULL << pde_shift) - 1); > + u64 end; > > WARN_ON(length == 0); > WARN_ON(offset_in_page(addr|length)); > @@ -439,22 +437,22 @@ static inline uint32_t i915_pte_count(uint64_t addr, > size_t length, > return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); > } > > -static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) > +static inline u32 i915_pde_index(u64 addr, u32 shift) > { > return (addr >> shift) & I915_PDE_MASK; > } > > -static inline uint32_t gen6_pte_index(uint32_t addr) > +static inline u32 gen6_pte_index(u32 addr) > { > return i915_pte_index(addr, GEN6_PDE_SHIFT); > } > > -static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) > +static inline u32 gen6_pte_count(u32 addr, u32 length) > { > return i915_pte_count(addr, length, GEN6_PDE_SHIFT); > } > > -static inline uint32_t gen6_pde_index(uint32_t addr) > +static inline u32 gen6_pde_index(u32 addr) > { > return i915_pde_index(addr, GEN6_PDE_SHIFT); > } > @@ -487,27 +485,27 @@ static inline uint32_t gen6_pde_index(uint32_t addr) > temp = min(temp - start, length); \ > start += temp, length -= temp; }), ++iter) > > -static inline uint32_t gen8_pte_index(uint64_t address) > +static inline u32 gen8_pte_index(u64 address) > { > return i915_pte_index(address, GEN8_PDE_SHIFT); > } > > -static inline uint32_t gen8_pde_index(uint64_t address) > +static inline u32 gen8_pde_index(u64 address) > { > return i915_pde_index(address, GEN8_PDE_SHIFT); > } > > -static inline uint32_t gen8_pdpe_index(uint64_t address) > +static inline u32 gen8_pdpe_index(u64 address) > { > return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; > } > > -static inline uint32_t gen8_pml4e_index(uint64_t address) > +static inline u32 gen8_pml4e_index(u64 address) > { > return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; > } > > -static inline size_t gen8_pte_count(uint64_t address, uint64_t length) > +static inline u64 gen8_pte_count(u64 address, u64 length) > { > return i915_pte_count(address, length, GEN8_PDE_SHIFT); > } > -- > 2.11.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
