On Tue, Jun 12, 2012 at 02:47:32PM -0700, Jesse Barnes wrote:
> ValleyView is similar to IbexPeak here, but with different register
> offsets.
> 
> Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 5006928..2a677f8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6772,7 +6772,24 @@ static void intel_setup_outputs(struct drm_device *dev)
>  
>               if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
>                       intel_dp_init(dev, PCH_DP_D);
> +     } else if (IS_VALLEYVIEW(dev)) {
> +             int found;
> +
> +             if (I915_READ(VLV_HDMIB) & PORT_DETECTED) {

VLV_HDMIB == SDVOB, which royally confused me, especially since below you
use SDVOC for VLV_HDMC. Yeah, pre-pch_split we just use the SDVO names for
the HDMI registers. I guess I'll just wait for Paulo to clean up this
mess.

> +                     /* SDVOB multiplex with HDMIB */
> +                     found = intel_sdvo_init(dev, VLV_HDMIB, true);
> +                     if (!found)
> +                             intel_hdmi_init(dev, VLV_HDMIB);
> +                     if (!found && (I915_READ(DP_B) & DP_DETECTED))
> +                             intel_dp_init(dev, DP_B);
> +             }
> +
> +             if (I915_READ(SDVOC) & PORT_DETECTED)
> +                     intel_hdmi_init(dev, SDVOC);
>  
> +             /* Shares lanes with HDMI on SDVOC */
> +             if (!dpd_is_edp && (I915_READ(DP_C) & DP_DETECTED))
> +                     intel_dp_init(dev, DP_C);

This !dpd_is_edp check here looks fishy for DP_C, copy&paste fail?

Also, I wonder where you set up the vlv eDP panels?

>       } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
>               bool found = false;
>  
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: dan...@ffwll.ch
Mobile: +41 (0)79 365 57 48
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to