On LPT onwards, there is only one FDI receiver, but any pipe can drive it.
For now, we consider that only pipeA can work in CRT mode, so if any other
pipe attempts to enable FDI receiver it is considered invalid behavior.
Signed-off-by: Eugeni Dodonov <eugeni.dodo...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 36 ++++++++++++++++++++++++++----------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 76508a7..e8fd6cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1128,14 +1128,23 @@ static void assert_fdi_rx(struct drm_i915_private
*dev_priv,
u32 val;
bool cur_state;
- if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
- DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe
> 0\n");
+ /* On LPT, there is only one FDI RX that can be used. At the same
+ * time, any pipe can connect to it, but only one at a time. To
+ * simplify the enabling, we consider that only pipeA can be used in
+ * FDI configuration.
+ */
+ if (HAS_PCH_LPT(dev_priv->dev)) {
+ if (pipe > 0) {
+ DRM_ERROR("Attempting to %s FDI_RX on Haswell pipe >
0\n",
+ (state==true) ? "enable" : "disable");
return;
- } else {
- reg = FDI_RX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_RX_ENABLE);
+ }
}
+
+ reg = FDI_RX_CTL(pipe);
+ val = I915_READ(reg);
+ cur_state = !!(val & FDI_RX_ENABLE);
+
WARN(cur_state != state,
"FDI RX state assertion failure (expected %s, current %s)\n",
state_string(state), state_string(cur_state));
@@ -1651,6 +1660,17 @@ static void intel_enable_transcoder(struct
drm_i915_private *dev_priv,
/* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5);
+ if (HAS_PCH_LPT(dev_priv->dev)) {
+ /* On LPT, there is only one transcoder, but any pipe can be
used with it.
+ * To simplify things, we consider that only pipeA can be used
with CRT,
+ * so we handle this check in the same way as with the FDI
receiver.
+ */
+ if (pipe > 0) {
+ DRM_ERROR("Attempting to enable transcoder on Lynx
point with pipe > 0\n");
+ return;
+ }
+ }
+
/* Make sure PCH DPLL is enabled */
assert_pch_pll_enabled(dev_priv,
to_intel_crtc(crtc)->pch_pll,
@@ -1660,10 +1680,6 @@ static void intel_enable_transcoder(struct
drm_i915_private *dev_priv,
assert_fdi_tx_enabled(dev_priv, pipe);
assert_fdi_rx_enabled(dev_priv, pipe);
- if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
- DRM_ERROR("Attempting to enable transcoder on Haswell with pipe
> 0\n");
- return;
- }
reg = TRANSCONF(pipe);
val = I915_READ(reg);
pipeconf_val = I915_READ(PIPECONF(pipe));
--
1.7.11.1
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