One warning is that in order to get DPLL Link rates 3240 and 4050 that allows 648000 and 810000 is that: "Some SKUs may require elevated I/O voltage to support this."
v2: Rebase on top of source_rates changes. Signed-off-by: Rodrigo Vivi <[email protected]> --- drivers/gpu/drm/i915/intel_dp.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b7adf0a..90d437ec 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -97,6 +97,9 @@ struct dp_link_dpll { 324000, 432000, 540000 }; static const int skl_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; +static const int cnl_rates[] = { 162000, 216000, 270000, + 324000, 432000, 540000, + 648000, 810000 }; static const int default_rates[] = { 162000, 270000, 540000 }; /** @@ -247,6 +250,9 @@ static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) if (IS_GEN9_LP(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); + } else if (IS_CANNONLAKE(dev_priv)) { + source_rates = cnl_rates; + size = ARRAY_SIZE(cnl_rates); } else if (IS_GEN9_BC(dev_priv)) { source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
