On ke, 2017-04-05 at 22:07 +0100, Chris Wilson wrote:
> When discussing a new WC mmap, we based the interface upon the
> assumption that GTT was fully coherent. How naive! Commits 3b5724d702ef
> ("drm/i915: Wait for writes through the GTT to land before reading
> back") and ed4596ea992d ("drm/i915/guc: WA to address the Ringbuffer
> coherency issue") demonstrate that writes through the GTT are indeed
> delayed and may be overtaken by direct WC access. To be safe, if
> userspace is mixing WC mmaps with other potential GTT access (pwrite,
> GTT mmaps) it should use set_domain(WC).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96563
> Testcase: igt/gem_pwrite/small-gtt*
> Testcase: igt/drv_selftest/coherency
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
<SNIP>
> +int
> +i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write)
> +{
> + int ret;
> +
> + lockdep_assert_held(&obj->base.dev->struct_mutex);
> +
> > + ret = i915_gem_object_wait(obj,
> > + I915_WAIT_INTERRUPTIBLE |
> > + I915_WAIT_LOCKED |
> + (write ? I915_WAIT_ALL : 0),
Could construct into flags variable.
> + /* Flush and acquire obj->pages so that we are coherent through
> + * direct access in memory with previous cached writes through
> + * shmemfs and that our cache domain tracking remains valid.
> + * For example, if the obj->filp was moved to swap without us
> + * being notified and releasing the pages, we would mistakenly
> + * continue to assume that the obj remained out of the CPU cached
> + * domain.
> + */
> + ret = i915_gem_object_pin_pages(obj);
> + if (ret)
> + return ret;
> +
> + i915_gem_object_flush_cpu_write_domain(obj);
> + i915_gem_object_flush_gtt_write_domain(obj);
I was thinking if WC should be a "substate" of CPU domain, because we
don't have i915_gem_object_flush_wc_write_domain.
Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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