On 05/05/2017 15:49, Ville Syrjälä wrote:
On Fri, May 05, 2017 at 12:43:21PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
It seems that the DMC likes to transition between the DC states
a lot when there are no connected displays (no active power
domains) during simple command submission.
Is it trapping on some interrupt register accesses or what? And
if so which registers are affected?
It looks like GT IIR or something along those lines it but I couldn't
say with total confidence. It is just a guess. Firmware binary
definitely "mentions" those registers as can be seen by inspecting it
with a hex editor.
The data I collected at least seems to present a correlation between the
batch frequency and DC state transition frequency:
tgt DC irqs irqs/s irq batch/s DC/s DC/batch
submit transitions /
freq batch
========================================================================
10000 20000 78300 7830.00 1.96 4000.00 2000.00 0.50
9901 14000 52855 7550.71 1.32 5714.29 2000.00 0.35
9524 13500 49100 7328.36 1.23 5970.15 2014.93 0.34
9091 13500 49200 7235.29 1.23 5882.35 1985.29 0.34
5000 16900 33290 3916.47 0.83 4705.88 1988.24 0.42
3333 27800 69550 4932.62 1.74 2836.88 1971.63 0.70
1667 57200 80200 2655.63 2.01 1324.50 1894.04 1.43
909 80000 80034 1482.11 2.00 740.74 1481.48 2.00
476 87000 80039 820.91 2.00 410.26 892.31 2.18
196 160000 80055 334.40 2.00 167.08 668.34 4.00
Submitted batches were ~100us long in all cases. So with low batch
frequency it looks pretty believable. For example when we have 167.08
batches/s, we have 334.40 irq/s - which is double - as expected for
execlists. And we get again double that in terms of DC transitions per
second. Each irq is one GT IIR write from the GPU side, and another from
the CPU side.
This was actually Imre's suggestion btw. Before I was only looking at
the irq/s to DC/s correlation which was confusing me a lot since there
are more of the latter, so I thought it can't be the trigger. But once
Imre mentioned the possibility that things are triggered by IIR register
writes numbers started making more sense.
Then with higher batch frequencies the ratio starts falling, is it
because DC transitions are too slow to keep up, or something else I am
not sure.
Regards,
Tvrtko
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