We can't mix 64K and 4K pte's in the same page-table, so for now we align 64K objects to 2M to avoid any potential mixing. This is potentially wasteful but in reality shouldn't be too bad since this only applies to the virtual address space of a 48b PPGTT.
Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Cc: Joonas Lahtinen <[email protected]> --- drivers/gpu/drm/i915/i915_vma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 53f6c94b2ee6..d2e8edd351cf 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -475,6 +475,15 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) obj->gtt_page_size > I915_GTT_PAGE_SIZE) { unsigned int page_alignment = obj->gtt_page_size; + /* We can't mix 64K and 4K pte's in the same page-table (2M + * block), and so to avoid the ugliness and complexity of + * coloring we opt for just aligning 64K objects to 2M. + */ + if (page_alignment == I915_GTT_PAGE_SIZE_64K) { + page_alignment = I915_GTT_PAGE_SIZE_2M; + size = roundup(size, page_alignment); + } + alignment = max_t(typeof(alignment), alignment, page_alignment); GEM_BUG_ON(!IS_ALIGNED(vma->size, obj->gtt_page_size)); } -- 2.9.4 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
