When inserting into a 48bit PPGTT we should the align the vma start address to the required page size boundary, to guarantee we use said page size in the gtt. If we are dealing with multiple page-sizes, we can't guarantee anything and just align to the largest. For soft pinning we don't force any alignment.
Signed-off-by: Matthew Auld <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Chris Wilson <[email protected]> --- drivers/gpu/drm/i915/i915_vma.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 1aba47024656..c355ccb01872 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -485,6 +485,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (ret) goto err_unpin; } else { + if (i915_vm_is_48bit(vma->vm) && + obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { + unsigned int page_alignment = obj->mm.page_sizes.sg; + + /* Align to the largest and hope for the best */ + if (!is_power_of_2(page_alignment)) + page_alignment = BIT(fls64(page_alignment)-1); + + alignment = max_t(typeof(alignment), alignment, + page_alignment); + } + ret = i915_gem_gtt_insert(vma->vm, &vma->node, size, alignment, obj->cache_level, start, end, flags); -- 2.9.4 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
