From: Ville Syrjälä <[email protected]> Here's yet another iteration of CCS support.
The first major change is that we now treat fb->offsets[] as raw byte offsets instead of linear offsets since that's what userspace seems to want. This means we'll not allow non-tile aligned offsets except with linear buffers. I still think non-tile aligned offsets are potentially useful for planar formats, but in order to support that we'd either need to pretend that the non-aligned part of the offset is a linear offset within the tile, or we'd need to deal with the actual internal structure of the tile. The other change is that we now use the LLC/eLLC hotspot avoidance hash mode. The spec is super confusing when it comes to documenting this. In places it claims that we needa to align everything to 2MiB, but in other places it seems to be telling us that we don't need to do that. I've tried to confirm this empirically by randomizing the ppgtt address between rendering to and sampling from the same compressed buffer, and so far I've not seen any corruption. The only minor caveat is that I've not tried this on a machine with eLLC. Series available here: git://github.com/vsyrjala/linux.git ccs_leftovers_2 Cc: Paulo Zanoni <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Jason Ekstrand <[email protected]> Cc: Daniel Stone <[email protected]> Ville Syrjälä (2): drm/i915: Implement .get_format_info() hook for CCS drm/i915: Add render decompression support drivers/gpu/drm/i915/i915_reg.h | 29 +++ drivers/gpu/drm/i915/intel_display.c | 386 ++++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_engine_cs.c | 13 ++ drivers/gpu/drm/i915/intel_pm.c | 29 ++- drivers/gpu/drm/i915/intel_sprite.c | 5 + include/uapi/drm/drm_fourcc.h | 20 ++ 6 files changed, 422 insertions(+), 60 deletions(-) -- 2.13.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
