On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
> There's no need to keep reading random registers in i915_swizzle_info if
> the platform is not doing GPU side swizzling.
>
> After HSW, swizzling is not used, and the CPU's memory controller
> performs all the address swizzling modifications, commit be292e1563ac5b
> ("drm/i915/bdw: Let the memory controller do all the swizzling").
But BDW still contains the registers and hardware capability no? So
might be a good idea to be able to check that it's not misconfigured.
>
> Cc: Daniele Ceraolo Spurio <[email protected]>
> Signed-off-by: Michel Thierry <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 87e13131f6ea..e82f503389fb 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2152,6 +2152,11 @@ static int i915_swizzle_info(struct seq_file *m, void
> *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>
> + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> + seq_puts(m, "not supported - CPU does all the swizzling\n");
> + return 0;
> + }
> +
> intel_runtime_pm_get(dev_priv);
>
> seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> --
> 2.11.0
>
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--
Ville Syrjälä
Intel OTC
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