On Fri, Jul 20, 2012 at 06:02:28PM +0100, Chris Wilson wrote: > The requirements for the sync flush to be emitted prior to the render > cache flush is only true for SandyBridge. On IvyBridge and friends we > can just emit the flushes with an inline CS stall. > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Since I've seen Ken ditch these w/a for ivb+ in mesa, I've figured that this is ok. Some bspec reading seems to agree. Merged to dinq, thanks for the patch. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
