[Intel-gfx] [PATCH 5/7] drm/i915: Program gen4 watermarks atomically

[Maarten Lankhorst]

We're already calculating the watermarks correctly, now we have to
program them too.

Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 25 +++++++++++++++----------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f2062f589f41..3484ce40f2b0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2266,20 +2266,20 @@ static int i965_compute_pipe_wm(struct intel_crtc_state 
*crtc_state)
        return 0;
 }
 
-static void i965_update_wm(struct intel_crtc *crtc)
+static void i965_program_watermarks(struct drm_i915_private *dev_priv)
 {
-       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+       struct intel_crtc *crtc;
+       struct i9xx_wm_state *wm_state = NULL;
        int srwm = 1;
        int cursor_sr = 16;
        bool cxsr_enabled = false;
 
-       crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal;
-
-       /* Calc sr entries for one plane configs */
        crtc = single_enabled_crtc(dev_priv);
-       if (crtc && crtc->wm.active.i9xx.cxsr) {
-               struct i9xx_wm_state *wm_state = &crtc->wm.active.i9xx;
+       if (crtc)
+               wm_state = &crtc->wm.active.i9xx;
 
+       /* Calc sr entries for one plane configs */
+       if (wm_state && wm_state->cxsr) {
                srwm = wm_state->sr.plane;
                cursor_sr = wm_state->sr.cursor;
 
@@ -2569,8 +2569,10 @@ static void i9xx_initial_watermarks(struct 
intel_atomic_state *state,
                pnv_program_watermarks(dev_priv);
        else if (INTEL_INFO(dev_priv)->num_pipes == 1)
                i845_program_watermarks(intel_crtc);
-       else
+       else if (INTEL_GEN(dev_priv) < 4)
                i9xx_program_watermarks(dev_priv);
+       else
+               i965_program_watermarks(dev_priv);
        mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -2589,8 +2591,10 @@ static void i9xx_optimize_watermarks(struct 
intel_atomic_state *state,
                pnv_program_watermarks(dev_priv);
        else if (INTEL_INFO(dev_priv)->num_pipes == 1)
                i845_program_watermarks(intel_crtc);
-       else
+       else if (INTEL_GEN(dev_priv) < 4)
                i9xx_program_watermarks(dev_priv);
+       else
+               i965_program_watermarks(dev_priv);
        mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
@@ -9019,7 +9023,8 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
                }
        } else if (IS_GEN4(dev_priv)) {
                dev_priv->display.compute_pipe_wm = i965_compute_pipe_wm;
-               dev_priv->display.update_wm = i965_update_wm;
+               dev_priv->display.initial_watermarks = i9xx_initial_watermarks;
+               dev_priv->display.optimize_watermarks = 
i9xx_optimize_watermarks;
        } else if (IS_GEN3(dev_priv)) {
                dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm;
                dev_priv->display.compute_intermediate_wm = 
i9xx_compute_intermediate_wm;
-- 
2.11.0

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