Chris Wilson <ch...@chris-wilson.co.uk> writes:

> As we may have just bound the renderstate into the GGTT for execution, we
> need to ensure that the GTT TLB are also flushed.
>
> On snb-gt2, this would cause a random GPU hang at the start of a new
> context (e.g. boot) and on snb-gt1, it was causing the renderstate batch
> to take ~10s. It was the GPU hang that revealed the truth, as the CS
> gleefully executed beyond the end of the golden renderstate batch, a good
> indicator for a GTT TLB miss.
>
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
> Cc: sta...@vger.kernel.org

The flush has been there but got stomped by:

Fixes: dc4be6071a24 ("drm/i915: Add explicit request management to 
i915_gem_init_hw()")

Now we can fix the gen6 renderstate too ;)

Reviewed-by: Mika Kuoppala <mika.kuopp...@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c 
> b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 241d827b85fb..3703dc91eeda 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -242,6 +242,10 @@ int i915_gem_render_state_emit(struct 
> drm_i915_gem_request *req)
>                       goto err_unpin;
>       }
>  
> +     ret = req->engine->emit_flush(req, EMIT_INVALIDATE);
> +     if (ret)
> +             goto err_unpin;
> +
>       ret = req->engine->emit_bb_start(req,
>                                        so->batch_offset, so->batch_size,
>                                        I915_DISPATCH_SECURE);
> -- 
> 2.13.3
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