WC is apparently not an option for CNL+ on GTT here.
Trying to use it we get hard hangs.

Credits-to: Ben Widawsky <benjamin.widaw...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 10aa7762d9a6..3019bf509e3d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2717,7 +2717,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 
size)
         * resort to an uncached mapping. The WC issue is easily caught by the
         * readback check when writing GTT PTE entries.
         */
-       if (IS_GEN9_LP(dev_priv))
+       if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10)
                ggtt->gsm = ioremap_nocache(phys_addr, size);
        else
                ggtt->gsm = ioremap_wc(phys_addr, size);
-- 
2.13.2

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