This patch is doing nover except reordering functions to highlight
changes in the next patch.
Change-Id: I0cd298780503ae8f6f8035b86c59fc8b5191356b
Signed-off-by: Dmitry Rogozhkin <dmitry.v.rogozh...@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Cc: Peter Zijlstra <pet...@infradead.org>
---
drivers/gpu/drm/i915/i915_pmu.c | 180 ++++++++++++++++++++--------------------
1 file changed, 90 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 3272ec0..bcdf2bc 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -363,6 +363,88 @@ static bool engine_needs_busy_stats(struct intel_engine_cs
*engine)
(engine->pmu.enable & BIT(I915_SAMPLE_BUSY));
}
+static u64 count_interrupts(struct drm_i915_private *i915)
+{
+ /* open-coded kstat_irqs() */
+ struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
+ u64 sum = 0;
+ int cpu;
+
+ if (!desc || !desc->kstat_irqs)
+ return 0;
+
+ for_each_possible_cpu(cpu)
+ sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
+
+ return sum;
+}
+
+static void i915_pmu_event_read(struct perf_event *event)
+{
+ struct drm_i915_private *i915 =
+ container_of(event->pmu, typeof(*i915), pmu.base);
+ u64 val = 0;
+
+ if (is_engine_event(event)) {
+ u8 sample = engine_event_sample(event);
+ struct intel_engine_cs *engine;
+
+ engine = intel_engine_lookup_user(i915,
+ engine_event_class(event),
+ engine_event_instance(event));
+
+ if (WARN_ON_ONCE(!engine)) {
+ /* Do nothing */
+ } else if (sample == I915_SAMPLE_BUSY &&
+ engine->pmu.busy_stats) {
+ val = ktime_to_ns(intel_engine_get_busy_time(engine));
+ } else {
+ val = engine->pmu.sample[sample];
+ }
+ } else switch (event->attr.config) {
+ case I915_PMU_ACTUAL_FREQUENCY:
+ val = i915->pmu.sample[__I915_SAMPLE_FREQ_ACT];
+ break;
+ case I915_PMU_REQUESTED_FREQUENCY:
+ val = i915->pmu.sample[__I915_SAMPLE_FREQ_REQ];
+ break;
+ case I915_PMU_ENERGY:
+ val = intel_energy_uJ(i915);
+ break;
+ case I915_PMU_INTERRUPTS:
+ val = count_interrupts(i915);
+ break;
+
+ case I915_PMU_RC6_RESIDENCY:
+ if (!i915->gt.awake)
+ return;
+
+ val = intel_rc6_residency_ns(i915,
+ IS_VALLEYVIEW(i915) ?
+ VLV_GT_RENDER_RC6 :
+ GEN6_GT_GFX_RC6);
+ break;
+
+ case I915_PMU_RC6p_RESIDENCY:
+ if (!i915->gt.awake)
+ return;
+
+ if (!IS_VALLEYVIEW(i915))
+ val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
+ break;
+
+ case I915_PMU_RC6pp_RESIDENCY:
+ if (!i915->gt.awake)
+ return;
+
+ if (!IS_VALLEYVIEW(i915))
+ val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+ break;
+ }
+
+ local64_set(&event->count, val);
+}
+
static void i915_pmu_enable(struct perf_event *event)
{
struct drm_i915_private *i915 =
@@ -440,23 +522,6 @@ static void i915_pmu_disable(struct perf_event *event)
i915_pmu_timer_cancel(event);
}
-static int i915_pmu_event_add(struct perf_event *event, int flags)
-{
- struct hw_perf_event *hwc = &event->hw;
-
- if (flags & PERF_EF_START)
- i915_pmu_enable(event);
-
- hwc->state = !(flags & PERF_EF_START);
-
- return 0;
-}
-
-static void i915_pmu_event_del(struct perf_event *event, int flags)
-{
- i915_pmu_disable(event);
-}
-
static void i915_pmu_event_start(struct perf_event *event, int flags)
{
i915_pmu_enable(event);
@@ -467,86 +532,21 @@ static void i915_pmu_event_stop(struct perf_event *event,
int flags)
i915_pmu_disable(event);
}
-static u64 count_interrupts(struct drm_i915_private *i915)
+static int i915_pmu_event_add(struct perf_event *event, int flags)
{
- /* open-coded kstat_irqs() */
- struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
- u64 sum = 0;
- int cpu;
+ struct hw_perf_event *hwc = &event->hw;
- if (!desc || !desc->kstat_irqs)
- return 0;
+ if (flags & PERF_EF_START)
+ i915_pmu_enable(event);
- for_each_possible_cpu(cpu)
- sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
+ hwc->state = !(flags & PERF_EF_START);
- return sum;
+ return 0;
}
-static void i915_pmu_event_read(struct perf_event *event)
+static void i915_pmu_event_del(struct perf_event *event, int flags)
{
- struct drm_i915_private *i915 =
- container_of(event->pmu, typeof(*i915), pmu.base);
- u64 val = 0;
-
- if (is_engine_event(event)) {
- u8 sample = engine_event_sample(event);
- struct intel_engine_cs *engine;
-
- engine = intel_engine_lookup_user(i915,
- engine_event_class(event),
- engine_event_instance(event));
-
- if (WARN_ON_ONCE(!engine)) {
- /* Do nothing */
- } else if (sample == I915_SAMPLE_BUSY &&
- engine->pmu.busy_stats) {
- val = ktime_to_ns(intel_engine_get_busy_time(engine));
- } else {
- val = engine->pmu.sample[sample];
- }
- } else switch (event->attr.config) {
- case I915_PMU_ACTUAL_FREQUENCY:
- val = i915->pmu.sample[__I915_SAMPLE_FREQ_ACT];
- break;
- case I915_PMU_REQUESTED_FREQUENCY:
- val = i915->pmu.sample[__I915_SAMPLE_FREQ_REQ];
- break;
- case I915_PMU_ENERGY:
- val = intel_energy_uJ(i915);
- break;
- case I915_PMU_INTERRUPTS:
- val = count_interrupts(i915);
- break;
-
- case I915_PMU_RC6_RESIDENCY:
- if (!i915->gt.awake)
- return;
-
- val = intel_rc6_residency_ns(i915,
- IS_VALLEYVIEW(i915) ?
- VLV_GT_RENDER_RC6 :
- GEN6_GT_GFX_RC6);
- break;
-
- case I915_PMU_RC6p_RESIDENCY:
- if (!i915->gt.awake)
- return;
-
- if (!IS_VALLEYVIEW(i915))
- val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
- break;
-
- case I915_PMU_RC6pp_RESIDENCY:
- if (!i915->gt.awake)
- return;
-
- if (!IS_VALLEYVIEW(i915))
- val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
- break;
- }
-
- local64_set(&event->count, val);
+ i915_pmu_disable(event);
}
static int i915_pmu_event_event_idx(struct perf_event *event)
--
1.8.3.1
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