On Tue, 2017-08-29 at 18:19 +0000, Wang, Zhi A wrote: > I see. > > For 1) I can fix it in the next RFC.
Please send a separate bugfix for this so we can proceed to test and merge immediately. Regards, Joonas > For 2) I can find some VPG guys to ask for the details. > > Thanks, > Zhi. > > -----Original Message----- > From: Chris Wilson [mailto:[email protected]] > Sent: Tuesday, August 29, 2017 9:14 PM > To: Wang, Zhi A <[email protected]>; Joonas Lahtinen > <[email protected]>; [email protected]; > [email protected] > Cc: [email protected]; Widawsky, Benjamin > <[email protected]>; Vivi, Rodrigo <[email protected]> > Subject: RE: [RFCv5 2/2] drm/i915: Introduce private PAT management > > Quoting Wang, Zhi A (2017-08-29 18:54:51) > > Another finding during the re-factoring are: > > > > a)It looks like that the PPAT_CACHE_INDEX on BDW/SKL is mapped to: > > GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0); > > > > But the PPAT_CACHE_INDEX on CNL is mapped to GEN8_PPAT_LLCELLC | > > GEN8_PPAT_AGE(0); > > > > GEN8_PPAT_WB is missing here and by default the cache attribute is UC. > > > > Is this set intentionally? > > That sounds like a nasty little bug. > > > b) Looks like all the ages of PPAT in windows driver is AGE(3) because of > > some performance gains, is there any reason that i915 has to set it to > > AGE(0)? > > Nope, it's never been rigorously tested. On occasion, we've swapped it around > (at least for the older gen) and never found a significant difference; I > haven't even heard if anyone has tried such experiments on gen8+. Off the top > of my head, the age should only matter when you have PTE with different ages > (unless there's some automatic clock algorithm tracking the age on each page > in a shadow, the challenge being then when you decide to refresh the age from > the PTE.) -Chris -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
