On Tue, Aug 29, 2017 at 04:22:25PM -0700, Rodrigo Vivi wrote: > Vswing sequences on BXT and CNL are equivalent > to the ddi buffer registers setting on other platforms. > > For some reason it got aligned with skl_ddi_set_iboost what > is semantically incorrect. This forced us to keep skipping > ddi buffer translation tables on the platforms that has > the vswing sequences. > > v2: Don't mess with DP signal levels on this patch. > > Cc: Vandana Kannan <[email protected]> > Cc: Imre Deak <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Cc: Ander Conselvan de Oliveira <[email protected]> > Signed-off-by: Rodrigo Vivi <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_ddi.c | 22 ++++++++++------------ > 1 file changed, 10 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 9a887780f99f..eedd29487e0b 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -688,9 +688,6 @@ static void intel_prepare_dp_ddi_buffers(struct > intel_encoder *encoder) > enum port port = intel_ddi_get_encoder_port(encoder); > const struct ddi_buf_trans *ddi_translations; > > - if (IS_GEN9_LP(dev_priv)) > - return; > - > switch (encoder->type) { > case INTEL_OUTPUT_EDP: > ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, > @@ -741,9 +738,6 @@ static void intel_prepare_hdmi_ddi_buffers(struct > intel_encoder *encoder) > enum port port = intel_ddi_get_encoder_port(encoder); > const struct ddi_buf_trans *ddi_translations_hdmi; > > - if (IS_GEN9_LP(dev_priv)) > - return; > - > hdmi_level = intel_ddi_hdmi_level(dev_priv, port); > > if (IS_GEN9_BC(dev_priv)) { > @@ -2154,7 +2148,9 @@ static void intel_ddi_pre_enable_dp(struct > intel_encoder *encoder, > > intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); > > - intel_prepare_dp_ddi_buffers(encoder); > + if (!IS_GEN9_LP(dev_priv) && !IS_CANNONLAKE(dev_priv)) > + intel_prepare_dp_ddi_buffers(encoder); > + > intel_ddi_init_dp_buf_reg(encoder); > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > intel_dp_start_link_train(intel_dp); > @@ -2180,14 +2176,16 @@ static void intel_ddi_pre_enable_hdmi(struct > intel_encoder *encoder, > > intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); > > - intel_prepare_hdmi_ddi_buffers(encoder); > - if (IS_GEN9_BC(dev_priv)) > - skl_ddi_set_iboost(encoder, level); > + if (IS_CANNONLAKE(dev_priv)) > + cnl_ddi_vswing_sequence(encoder, level); > else if (IS_GEN9_LP(dev_priv)) > bxt_ddi_vswing_sequence(dev_priv, level, port, > INTEL_OUTPUT_HDMI); > - else if (IS_CANNONLAKE(dev_priv)) > - cnl_ddi_vswing_sequence(encoder, level); > + else > + intel_prepare_hdmi_ddi_buffers(encoder); > + > + if (IS_GEN9_BC(dev_priv)) > + skl_ddi_set_iboost(encoder, level); > > intel_dig_port->set_infoframes(&encoder->base, > has_infoframe, > -- > 2.13.2 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
