On Fri, 2017-09-01 at 18:12 +0100, Lionel Landwerlin wrote: > From: Chris Wilson <[email protected]> > > We want to allow userspace to reconfigure the subslice configuration for > its own use case. To do so, we expose a context parameter to allow > adjustment of the RPCS register stored within the context image (and > currently not accessible via LRI). If the context is adjusted before > first use, the adjustment is for "free"; otherwise if the context is > active we flush the context off the GPU (stalling all users) and forcing > the GPU to save the context to memory where we can modify it and so > ensure that the register is reloaded on next execution. > > The overhead of managing additional EU subslices can be significant, > especially in multi-context workloads. Non-GPGPU contexts should > preferably disable the subslices it is not using, and others should > fine-tune the number to match their workload. > > We expose complete control over the RPCS register, allowing > configuration of slice/subslice, via masks packed into a u64 for > simplicity. For example, > > struct drm_i915_gem_context_param arg; > > memset(&arg, 0, sizeof(arg)); > arg.ctx_id = ctx; > arg.param = I915_CONTEXT_PARAM_SSEU; > if (drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg) == 0) { > union drm_i915_gem_context_param_sseu *sseu = &arg.value; > > sseu->packed.subslice_mask = 0; > > drmIoctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg); > } > > could be used to disable all subslices where supported. > > v2: Fix offset of CTX_R_PWR_CLK_STATE in intel_lr_context_set_sseu() (Lionel) > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100899 > Signed-off-by: Chris Wilson <[email protected]> > Signed-off-by: Lionel Landwerlin <[email protected]> > Cc: Dmitry Rogozhkin <[email protected]> > CC: Tvrtko Ursulin <[email protected]> > CC: Zhipeng Gong <[email protected]> > CC: Joonas Lahtinen <[email protected]>
Please do link to the userspace patches, will be easier to track them that way. Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
