Re: [Intel-gfx] [PATCH] drm/i915: Transform WaInPlaceDecompressionHang to a simple reg write

[Oscar Mateo]

On 09/07/2017 02:30 AM, Mika Kuoppala wrote:
Oscar Mateo <oscar.ma...@intel.com> writes:

Hey Mika,

Regarding this patch: is there a consensus on where is the most
appropriate place to apply workarounds? My understanding is that
per-context workarounds (WAS_SET_BIT, etc...) go in
xxx_init_workarounds, while those that are needed only during
initialization (I915_WRITE) go in xxx_init_clock_gating. But it doesn't
look like this general rule is being followed (probably because
xxx_init_clock_gating is a very misleading name?).

This has probably been discussed before, so it would be good if we could
document the answer somewhere (maybe it already is?).

Yep, xxx_init_workarounds for per context. init_clock_gating for
globals.

If I recall init_clock_gating was a just suitable spot wrt
to init/reset to inject globals.

Have we reached the pain treshold and move to genx_workarounds.c
where there are per context and global entries?

-Mika


I don't know about several genX_workarounds.c, but at least one 
intel_workarounds.c where per-context and global entries live in harmony 
(maybe WABB stuff as well?).

-- Oscar

Thanks,

Oscar



On 09/06/2017 02:12 PM, Oscar Mateo wrote:
Afaict, GEN9_GAMT_ECO_REG_RW_IA does not live in the context, so writing
it on every context creation is overkill (and wrong).

Cc: Mika Kuoppala <mika.kuopp...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
---
   drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++++++++++++++----------
   1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c 
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 23812ec..9f01a5c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -985,8 +985,9 @@ static int skl_init_workarounds(struct intel_engine_cs 
*engine)
   
   	/* WaInPlaceDecompressionHang:skl */
        if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
-               WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                          GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+               I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                          (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                           GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
   
   	/* WaDisableLSQCROPERFforOCL:skl */
        ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1059,8 +1060,9 @@ static int bxt_init_workarounds(struct intel_engine_cs 
*engine)
   
   	/* WaInPlaceDecompressionHang:bxt */
        if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
-               WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                          GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+               I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                          (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                           GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
   
   	return 0;
   }
@@ -1089,8 +1091,9 @@ static int cnl_init_workarounds(struct intel_engine_cs 
*engine)
                                  GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE);
   
   	/* WaInPlaceDecompressionHang:cnl */
-       WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+       I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
   
   	/* WaPushConstantDereferenceHoldDisable:cnl */
        WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
@@ -1143,8 +1146,9 @@ static int kbl_init_workarounds(struct intel_engine_cs 
*engine)
                GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
   
   	/* WaInPlaceDecompressionHang:kbl */
-       WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+       I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
   
   	/* WaDisableLSQCROPERFforOCL:kbl */
        ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
@@ -1196,8 +1200,9 @@ static int cfl_init_workarounds(struct intel_engine_cs 
*engine)
                GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
   
   	/* WaInPlaceDecompressionHang:cfl */
-       WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
-                  GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
+       I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+                  (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+                   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
   
   	return 0;
   }
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