Em Ter, 2017-09-26 às 12:43 -0700, Rodrigo Vivi escreveu:
> This is heavily based on a initial patch provided by Ville
> plus all changes provided later by Ander.
>
> As Geminilake, Cannonlake also supports 2 pixels per clock.
>
> Different from Geminilake we are not implementing the 99% Wa.
> But we can revisit that decision later if we find out
> any limitation on later CNL SKUs.
>
> v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track
> minimum acceptable cdclk instead of "minimum dotclock")'
Reviewed-by: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 7 +------
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> 3 files changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c
> b/drivers/gpu/drm/i915/intel_cdclk.c
> index d6befabd6ed5..eabaf57b83ef 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1995,12 +1995,7 @@ static int intel_compute_max_dotclk(struct
> drm_i915_private *dev_priv)
> int max_cdclk_freq = dev_priv->max_cdclk_freq;
>
> if (INTEL_GEN(dev_priv) >= 10)
> - /*
> - * FIXME: Allow '2 * max_cdclk_freq'
> - * once DDI clock voltage requirements are
> - * handled correctly.
> - */
> - return max_cdclk_freq;
> + return 2 * max_cdclk_freq;
> else if (IS_GEMINILAKE(dev_priv))
> /*
> * FIXME: Limiting to 99% as a temporary workaround.
> See
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 026fa5460fe5..487b43ba3139 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12801,7 +12801,7 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *crtc_state
> crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> max_dotclk = to_intel_atomic_state(crtc_state->base.state)-
> >cdclk.logical.cdclk;
>
> - if (IS_GEMINILAKE(dev_priv))
> + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> max_dotclk *= 2;
>
> if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index c66af09e27a7..52c4c194aa51 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct
> intel_crtc_state *crtc_state)
> int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *cstate)
> {
> + struct drm_i915_private *dev_priv = to_i915(intel_crtc-
> >base.dev);
> struct drm_crtc_state *crtc_state = &cstate->base;
> struct drm_atomic_state *state = crtc_state->state;
> struct drm_plane *plane;
> @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct
> intel_crtc *intel_crtc,
> crtc_clock = crtc_state->adjusted_mode.crtc_clock;
> dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
>
> - if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)))
> + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
> dotclk *= 2;
>
> pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk,
> pipe_downscale);
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