Now that we can keep track of what ports we have dequeued, submit only those ports instead of iterating through all ports.
v2: s/coalesce/submit (Michał) v3: rebase to new naming Cc: Michał Winiarski <[email protected]> Cc: Chris Wilson <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Michał Winiarski <[email protected]> --- drivers/gpu/drm/i915/i915_guc_submission.c | 31 +++++++++++++++++------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 9 +++++++++ 2 files changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index d6071396da32..093211e74ad4 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -485,11 +485,13 @@ static void guc_ring_doorbell(struct i915_guc_client *client) /** * i915_guc_submit() - Submit commands through GuC * @engine: engine associated with the commands + * @first: index of first execlist port to start coalescing from * * The only error here arises if the doorbell hardware isn't functioning * as expected, which really shouldn't happen. */ -static void i915_guc_submit(struct intel_engine_cs *engine) +static void i915_guc_submit(struct intel_engine_cs *engine, + const unsigned int first) { struct drm_i915_private *dev_priv = engine->i915; struct intel_guc *guc = &dev_priv->guc; @@ -498,7 +500,7 @@ static void i915_guc_submit(struct intel_engine_cs *engine) const unsigned int engine_id = engine->id; unsigned int n; - for (n = 0; n < execlists_active_ports(execlists); n++) { + for (n = first; n < execlists_active_ports(execlists); n++) { struct execlist_port *port; struct drm_i915_gem_request *rq; unsigned int count; @@ -506,21 +508,22 @@ static void i915_guc_submit(struct intel_engine_cs *engine) port = execlists_port(execlists, n); rq = port_unpack(port, &count); - if (rq && count == 0) { - port_set(port, port_pack(rq, ++count)); + GEM_BUG_ON(!rq); + GEM_BUG_ON(count); - if (i915_vma_is_map_and_fenceable(rq->ring->vma)) - POSTING_READ_FW(GUC_STATUS); + port_set(port, port_pack(rq, ++count)); - spin_lock(&client->wq_lock); + if (i915_vma_is_map_and_fenceable(rq->ring->vma)) + POSTING_READ_FW(GUC_STATUS); - guc_wq_item_append(client, rq); - guc_ring_doorbell(client); + spin_lock(&client->wq_lock); - client->submissions[engine_id] += 1; + guc_wq_item_append(client, rq); + guc_ring_doorbell(client); - spin_unlock(&client->wq_lock); - } + client->submissions[engine_id] += 1; + + spin_unlock(&client->wq_lock); } } @@ -567,6 +570,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine) struct drm_i915_gem_request *last = NULL; bool submit = false; struct rb_node *rb; + unsigned int first_idx; spin_lock_irq(&engine->timeline->lock); rb = execlists->first; @@ -576,6 +580,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine) goto done; port = execlists_request_port(execlists); + first_idx = execlists_port_index(execlists, port); do { struct i915_priolist *p = rb_entry(rb, typeof(*p), node); @@ -615,7 +620,7 @@ static void i915_guc_dequeue(struct intel_engine_cs *engine) execlists->first = rb; if (submit) { port_assign(port, last); - i915_guc_submit(engine); + i915_guc_submit(engine, first_idx); } spin_unlock_irq(&engine->timeline->lock); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index c09d1c93fd15..5adf6d023f3e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -557,6 +557,15 @@ execlists_port(struct intel_engine_execlists * const execlists, return &execlists->port[port_n(execlists, n)]; } +static inline unsigned int +execlists_port_index(const struct intel_engine_execlists * const execlists, + const struct execlist_port * const port) +{ + const unsigned int n = port_index(port, execlists); + + return __port_n(n, -execlists->port_head, execlists->port_mask); +} + static inline struct execlist_port * execlists_port_head(struct intel_engine_execlists * const execlists) { -- 2.11.0 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
