On Sat, 2017-09-30 at 13:57 +0800, Weinan Li wrote:
> Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
> the host support this feature, need to check the BIT(3) of caps in PVINFO.
>
> Signed-off-by: Weinan Li <[email protected]>
> Cc: Chris Wilson <[email protected]>
<SNIP>
> @@ -396,6 +393,12 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
> if (intel_vtd_active())
> return true;
>
> + /* GVT emulation depends upon host kernel implementation, check
> + * support capbility by reading PV INFO before access HWSP.
> + */
The comment can be dropped completely, the code is self-descriptive.
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -722,7 +722,12 @@ static void intel_lrc_irq_handler(unsigned long data)
> &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> unsigned int head, tail;
>
> - /* However GVT emulation depends upon intercepting CSB mmio */
> + /* However GVT-g emulation depends upon host kernel
> + * implementation, need to check support capbility by reading PV
> + * INFO before access HWSP. Beside from this, another special
> + * configuration may also need to force use mmio, like IOMMU
> + * enabled.
> + */
s/capbility/capability/ and please rephrase this to be a kerneldoc for
csb_use_mmio at the declaration.
> if (unlikely(execlists->csb_use_mmio)) {
> buf = (u32 * __force)
> (dev_priv->regs +
> i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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