The number of PML4Es per PML4 and the number of PDPEs per PDP
should not be confused (even if the amount, 512, is indeed the
same).
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@intel.com>
Cc: Chris Wilson <ch...@chris-wsilon.co.uk>
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 93211a9..717bbd6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -124,6 +124,7 @@
* 47:39 | 38:30 | 29:21 | 20:12 | 11:0
* PML4E | PDPE | PDE | PTE | offset
*/
+#define GEN8_4LVL_PDPES 512
#define GEN8_PML4ES_PER_PML4 512
#define GEN8_PML4E_SHIFT 39
#define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
@@ -488,7 +489,7 @@ static inline u32 gen6_pde_index(u32 addr)
i915_pdpes_per_pdp(const struct i915_address_space *vm)
{
if (i915_vm_is_48bit(vm))
- return GEN8_PML4ES_PER_PML4;
+ return GEN8_4LVL_PDPES;
return GEN8_3LVL_PDPES;
}
--
1.9.1
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