On Wed, Sep 19, 2012 at 01:29:00PM -0700, Jesse Barnes wrote: > Workaround for dual port PS dispatch on GT1. > > Signed-off-by: Jesse Barnes <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e570aea..e863973 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4249,6 +4249,10 @@ > #define GEN7_L3LOG_BASE 0xB070 > #define GEN7_L3LOG_SIZE 0x80 > > +#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */ > +#define GEN7_HALF_SLICE_CHICKEN1_IVB 0xf100 > +#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3) > + > #define G4X_AUD_VID_DID 0x62020 > #define INTEL_AUDIO_DEVCL 0x808629FB > #define INTEL_AUDIO_DEVBLC 0x80862801 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 372a398..f860cdd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3537,6 +3537,17 @@ static void ivybridge_init_clock_gating(struct > drm_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > + /* WaDisablePSDDualDispatchEnable */ > + if (dev->pci_device == 0x0156 || > + dev->pci_device == 0x0152)
Can we please have a comment here explaining which pci ids we're matching here? Just in case we add yet another variant sometime. Or just plainly use IS_MOBILE, which seems to match here ... -Daniel > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + else > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_IVB, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + > _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > @@ -3618,6 +3629,11 @@ static void valleyview_init_clock_gating(struct > drm_device *dev) > CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > CHICKEN3_DGMG_DONE_FIX_DISABLE); > > + /* WaDisablePSDDualDispatchEnable */ > + I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, > + I915_READ(GEN7_HALF_SLICE_CHICKEN1) | > + _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); > + > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
