On Mon, Nov 27, 2017 at 08:16:15AM +0000, Valtteri Rantala wrote:
> Testing the texture read performance shows that the same tuning for
> the SQ credits is needed on GLK as on BXT/APL. This has been also
> confirmed by Altug from the HW team.
>
> V3: Rebase + fix
> Signed-off-by: Valtteri Rantala <valtteri.rant...@intel.com>
It also matches wa_database, so:
Reviewed-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> b/drivers/gpu/drm/i915/intel_engine_cs.c
> index fede62d..a9c1053 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct
> intel_engine_cs *engine)
> /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>
> + /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> + if (IS_GEN9_LP(dev_priv)) {
> + u32 val = I915_READ(GEN8_L3SQCREG1);
> +
> + val &= ~L3_PRIO_CREDITS_MASK;
> + val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> + I915_WRITE(GEN8_L3SQCREG1, val);
> + }
> +
> /* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
> I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> GEN8_LQSC_FLUSH_COHERENT_LINES));
> @@ -1199,12 +1208,6 @@ static int bxt_init_workarounds(struct intel_engine_cs
> *engine)
> I915_WRITE(FF_SLICE_CS_CHICKEN2,
>
> _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
>
> - /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> - val = I915_READ(GEN8_L3SQCREG1);
> - val &= ~L3_PRIO_CREDITS_MASK;
> - val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> - I915_WRITE(GEN8_L3SQCREG1, val);
> -
> /* WaToEnableHwFixForPushConstHWBug:bxt */
> WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> --
> 2.7.4
>
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> Intel-gfx@lists.freedesktop.org
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