2012/10/4 Damien Lespiau <[email protected]>: > From: Damien Lespiau <[email protected]> > > This workaround is only valid for IVB and VLV and the write triggers an > error on HSW.
In other words: the register does not exist anymore. It would be nice if we could volunteer someone to check the other workarounds on the same function. The registers may exist but the WAs may not be needed anymore. Reviewed-by: Paulo Zanoni <[email protected]> > > Signed-off-by: Damien Lespiau <[email protected]> > Cc: Paulo Zanoni <[email protected]> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ---- > 1 files changed, 0 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 3d219ec..d0403e8 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3479,10 +3479,6 @@ static void haswell_init_clock_gating(struct > drm_device *dev) > I915_WRITE(_3D_CHICKEN3, > _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); > > - I915_WRITE(IVB_CHICKEN3, > - CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > - CHICKEN3_DGMG_DONE_FIX_DISABLE); > - > /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > -- > 1.7.7.5 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
