Zero and One are additional commonly used values that can have its own definitions.
Signed-off-by: Michal Wajdeczko <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Joonas Lahtinen <[email protected]> --- drivers/gpu/drm/i915/fixed16_16.h | 15 ++++++++++++--- drivers/gpu/drm/i915/intel_pm.c | 22 +++++++++++----------- 2 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/fixed16_16.h b/drivers/gpu/drm/i915/fixed16_16.h index ec859c0..af23997 100644 --- a/drivers/gpu/drm/i915/fixed16_16.h +++ b/drivers/gpu/drm/i915/fixed16_16.h @@ -31,9 +31,18 @@ u32 val; } fixed16_16_t; -#define FP_16_16_MAX ({ \ - fixed16_16_t fp; \ - fp.val = UINT_MAX; \ +#define FIXED16_16_ZERO ({ \ + fixed16_16_t fp = { .val = 0 }; \ + fp; \ +}) + +#define FIXED16_16_ONE ({ \ + fixed16_16_t fp = { .val = 1 << 16 }; \ + fp; \ +}) + +#define FIXED16_16_MAX ({ \ + fixed16_16_t fp = { .val = UINT_MAX }; \ fp; \ }) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 5dccbf9..e400672 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3877,7 +3877,7 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, fixed16_16_t downscale_h, downscale_w; if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) - return u32_to_fixed16(0); + return FIXED16_16_ZERO; /* n.b., src is 16.16 fixed point, dst is whole integer */ if (plane->id == PLANE_CURSOR) { @@ -3903,8 +3903,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, fp_w_ratio = div_fixed16(src_w, dst_w); fp_h_ratio = div_fixed16(src_h, dst_h); - downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1)); - downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1)); + downscale_w = max_fixed16(fp_w_ratio, FIXED16_16_ONE); + downscale_h = max_fixed16(fp_h_ratio, FIXED16_16_ONE); return mul_fixed16(downscale_w, downscale_h); } @@ -3912,7 +3912,7 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, static fixed16_16_t skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state) { - fixed16_16_t pipe_downscale = u32_to_fixed16(1); + fixed16_16_t pipe_downscale = FIXED16_16_ONE; if (!crtc_state->base.enable) return pipe_downscale; @@ -3933,8 +3933,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, fp_w_ratio = div_fixed16(src_w, dst_w); fp_h_ratio = div_fixed16(src_h, dst_h); - downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1)); - downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1)); + downscale_w = max_fixed16(fp_w_ratio, FIXED16_16_ONE); + downscale_h = max_fixed16(fp_h_ratio, FIXED16_16_ONE); pipe_downscale = mul_fixed16(downscale_w, downscale_h); } @@ -3954,7 +3954,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, int crtc_clock, dotclk; uint32_t pipe_max_pixel_rate; fixed16_16_t pipe_downscale; - fixed16_16_t max_downscale = u32_to_fixed16(1); + fixed16_16_t max_downscale = FIXED16_16_ONE; if (!cstate->base.enable) return 0; @@ -4317,7 +4317,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, fixed16_16_t ret; if (latency == 0) - return FP_16_16_MAX; + return FIXED16_16_MAX; wm_intermediate_val = latency * pixel_rate * cpp; ret = div_fixed16(wm_intermediate_val, 1000 * 512); @@ -4337,7 +4337,7 @@ static fixed16_16_t skl_wm_method2(uint32_t pixel_rate, fixed16_16_t ret; if (latency == 0) - return FP_16_16_MAX; + return FIXED16_16_MAX; wm_intermediate_val = latency * pixel_rate; wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, @@ -4354,12 +4354,12 @@ static fixed16_16_t skl_wm_method2(uint32_t pixel_rate, fixed16_16_t linetime_us; if (!cstate->base.active) - return u32_to_fixed16(0); + return FIXED16_16_ZERO; pixel_rate = cstate->pixel_rate; if (WARN_ON(pixel_rate == 0)) - return u32_to_fixed16(0); + return FIXED16_16_ZERO; crtc_htotal = cstate->base.adjusted_mode.crtc_htotal; linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate); -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
