On Thu, 21 Dec 2017, Ville Syrjala <[email protected]> wrote:
> From: Ville Syrjälä <[email protected]>
>
> Gen9+ need to disable GMBUS clock gating when doing multi part
> transfers. Otherwise clock gating will kick in when GMBUS is in
> the WAIT state and presumably that will corrupt the transfer.
> This is documented as Display WA #0868.
>
> Apparently older hardware doesn't allow clock gating in the WAIT
> state and thus are unaffected by this problem.
>
> v2: Limit the PCH w/a to gen9 and gen10 only (DK)
> Actually change it to check the PCH type instead since
> it's the PCH that actually contains the GMBUS hardware
>
> Signed-off-by: Ville Syrjälä <[email protected]>
> Reviewed-by: Dhinakaran Pandiyan <[email protected]> #v1
Why wasn't this cc: stable? Should it have been?
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_i2c.c | 40
> ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb05849eabab..41285bec8fc0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3859,6 +3859,9 @@ enum {
> #define PWM2_GATING_DIS (1 << 14)
> #define PWM1_GATING_DIS (1 << 13)
>
> +#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
> +#define BXT_GMBUS_GATING_DIS (1 << 14)
> +
> #define _CLKGATE_DIS_PSL_A 0x46520
> #define _CLKGATE_DIS_PSL_B 0x46524
> #define _CLKGATE_DIS_PSL_C 0x46528
> @@ -7557,6 +7560,7 @@ enum {
> #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN,
> _FDI_RXB_CHICKEN)
>
> #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> +#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1<<31)
> #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
> #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
> #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> b/drivers/gpu/drm/i915/intel_i2c.c
> index a8c08994f505..ef9f91a0b0c9 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -142,6 +142,32 @@ static void pnv_gmbus_clock_gating(struct
> drm_i915_private *dev_priv,
> I915_WRITE(DSPCLK_GATE_D, val);
> }
>
> +static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + u32 val;
> +
> + val = I915_READ(SOUTH_DSPCLK_GATE_D);
> + if (!enable)
> + val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
> + else
> + val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> +}
> +
> +static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
> + bool enable)
> +{
> + u32 val;
> +
> + val = I915_READ(GEN9_CLKGATE_DIS_4);
> + if (!enable)
> + val |= BXT_GMBUS_GATING_DIS;
> + else
> + val &= ~BXT_GMBUS_GATING_DIS;
> + I915_WRITE(GEN9_CLKGATE_DIS_4, val);
> +}
> +
> static u32 get_reserved(struct intel_gmbus *bus)
> {
> struct drm_i915_private *dev_priv = bus->dev_priv;
> @@ -484,6 +510,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct
> i2c_msg *msgs, int num)
> int i = 0, inc, try = 0;
> int ret = 0;
>
> + /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> + if (IS_GEN9_LP(dev_priv))
> + bxt_gmbus_clock_gating(dev_priv, false);
> + else if (HAS_PCH_SPT(dev_priv) ||
> + HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
> + pch_gmbus_clock_gating(dev_priv, false);
> +
> retry:
> I915_WRITE_FW(GMBUS0, bus->reg0);
>
> @@ -585,6 +618,13 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct
> i2c_msg *msgs, int num)
> ret = -EAGAIN;
>
> out:
> + /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
> + if (IS_GEN9_LP(dev_priv))
> + bxt_gmbus_clock_gating(dev_priv, true);
> + else if (HAS_PCH_SPT(dev_priv) ||
> + HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
> + pch_gmbus_clock_gating(dev_priv, true);
> +
> return ret;
> }
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
