Reviewed-by: Jason Ekstrand <[email protected]> On Fri, Jan 19, 2018 at 6:41 AM, Ville Syrjala < [email protected]> wrote:
> From: Ville Syrjälä <[email protected]> > > Let's document why we claim hsub==8,vsub==16 for CCS. > > v2: Replace my explanation with Jason's > > Cc: Daniel Vetter <[email protected]> > Cc: Ben Widawsky <[email protected]> > Cc: Jason Ekstrand <[email protected]> > Cc: Daniel Stone <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 91f3c0a64596..8d0d5d8753c0 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2387,6 +2387,20 @@ static unsigned int > intel_fb_modifier_to_tiling(uint64_t > fb_modifier) > } > } > > +/* > + * From the Sky Lake PRM: > + * "The Color Control Surface (CCS) contains the compression status of > + * the cache-line pairs. The compression state of the cache-line pair > + * is specified by 2 bits in the CCS. Each CCS cache-line represents > + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled > + * cache-line-pairs. CCS is always Y tiled." > + * > + * Since cache line pairs refers to horizontally adjacent cache lines, > + * each cache line in the CCS corresponds to an area of 32x16 cache > + * lines on the main surface. Since each pixel is 4 bytes, this gives > + * us a ratio of one byte in the CCS for each 8x16 pixels in the > + * main surface. > + */ > static const struct drm_format_info ccs_formats[] = { > { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, > .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, > -- > 2.13.6 > >
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