From: Damien Lespiau <[email protected]>

With the consolidated registers, it appears that we're setting the same
bis several times. Let's just collect the bit we want to set and program
it once.

Signed-off-by: Damien Lespiau <[email protected]>
---
 drivers/gpu/drm/i915/intel_pm.c |   15 ++++-----------
 1 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 76e10c0..be42b2c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3316,8 +3316,6 @@ static void ironlake_init_clock_gating(struct drm_device 
*dev)
        I915_WRITE(PCH_3DCGDIS1,
                   VFMUNIT_CLOCK_GATE_DISABLE);
 
-       I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
-
        /*
         * According to the spec the following bits should be set in
         * order to enable memory self-refresh
@@ -3328,9 +3326,7 @@ static void ironlake_init_clock_gating(struct drm_device 
*dev)
        I915_WRITE(ILK_DISPLAY_CHICKEN2,
                   (I915_READ(ILK_DISPLAY_CHICKEN2) |
                    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
-       I915_WRITE(ILK_DSPCLK_GATE_D,
-                  (I915_READ(ILK_DSPCLK_GATE_D) |
-                   ILK_DPARBUNIT_CLOCK_GATE_DISABLE));
+       dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_DISABLE;
        I915_WRITE(DISP_ARB_CTL,
                   (I915_READ(DISP_ARB_CTL) |
                    DISP_FBC_WM_DIS));
@@ -3343,7 +3339,7 @@ static void ironlake_init_clock_gating(struct drm_device 
*dev)
         * should be set unconditionally in order to enable FBC.
         * The bit 22 of 0x42000
         * The bit 22 of 0x42004
-        * The bit 7,8,9 of 0x42020.
+        * The bit 7,8,9 of 0x42020 (dspclk_gate is set above)
         */
        if (IS_IRONLAKE_M(dev)) {
                I915_WRITE(ILK_DISPLAY_CHICKEN1,
@@ -3352,13 +3348,10 @@ static void ironlake_init_clock_gating(struct 
drm_device *dev)
                I915_WRITE(ILK_DISPLAY_CHICKEN2,
                           I915_READ(ILK_DISPLAY_CHICKEN2) |
                           ILK_DPARB_GATE);
-               I915_WRITE(ILK_DSPCLK_GATE_D,
-                          I915_READ(ILK_DSPCLK_GATE_D) |
-                          ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
-                          ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
-                          ILK_DPFDUNIT_CLOCK_GATE_DISABLE);
        }
 
+       I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
+
        I915_WRITE(ILK_DISPLAY_CHICKEN2,
                   I915_READ(ILK_DISPLAY_CHICKEN2) |
                   ILK_ELPIN_409_SELECT);
-- 
1.7.7.5

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