According to bspec, result_lines > 31 is only a maximum for latency
level 1 through 7.
For level 0 the number of lines is ignored, so always write 0 there
to prevent overflowing the 5 bits value.
This is required to make NV12 work.
Changes since v1:
- Rebase on top of GEN11 wm changes. It seems to use res_lines for
level 0 limit calculations, but still doesn't appear to program it.
Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> #v1
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb68abf6a8e9..41f26ab46501 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4596,7 +4596,8 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
min_disp_buf_needed = res_blocks;
}
- if (res_blocks >= ddb_allocation || res_lines > 31 ||
+ if ((level > 0 && res_lines > 31) ||
+ res_blocks >= ddb_allocation ||
min_disp_buf_needed >= ddb_allocation) {
*enabled = false;
@@ -4617,8 +4618,9 @@ static int skl_compute_plane_wm(const struct
drm_i915_private *dev_priv,
}
}
+ /* The number of lines are ignored for the level 0 watermark. */
+ *out_lines = level ? res_lines : 0;
*out_blocks = res_blocks;
- *out_lines = res_lines;
*enabled = true;
return 0;
--
2.15.1
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