Chris Wilson <ch...@chris-wilson.co.uk> writes: > Although the mmio are uncached and so should be flushed on every write, > be paranoid and do a mmio read after setting the ring head/tail to be > sure they have taken effect before moving on. > > v2: post tail to be pleasing to the eye > > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> > Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
This amount paranoia is warranted and clearly noted so, Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_uncore.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c > b/drivers/gpu/drm/i915/intel_uncore.c > index 164dbb8cfa36..0fd59dd6bbb5 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1522,9 +1522,11 @@ static void gen3_stop_engine(struct intel_engine_cs > *engine) > engine->name); > > I915_WRITE_FW(RING_HEAD(base), I915_READ_FW(RING_TAIL(base))); > + POSTING_READ_FW(RING_HEAD(base)); /* paranoia */ > > I915_WRITE_FW(RING_HEAD(base), 0); > I915_WRITE_FW(RING_TAIL(base), 0); > + POSTING_READ_FW(RING_TAIL(base)); > > /* The ring must be empty before it is disabled */ > I915_WRITE_FW(RING_CTL(base), 0); > -- > 2.16.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
