== Series Details ==
Series: Adding NV12 support (rev10)
URL : https://patchwork.freedesktop.org/series/28103/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6e8ea1c042eb drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_pm.c:5048:
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+ struct skl_ddb_values *src,
total: 0 errors, 0 warnings, 1 checks, 68 lines checked
30eb3a788144 drm/i915/skl+: refactor WM calculation for NV12
-:177: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#177: FILE: drivers/gpu/drm/i915/intel_pm.c:4164:
+ uint16_t *minimum, uint16_t *uv_minimum)
-:195: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#195: FILE: drivers/gpu/drm/i915/intel_pm.c:4197:
+ uint16_t uv_minimum[I915_MAX_PLANES] = {};
-:244: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#244: FILE: drivers/gpu/drm/i915/intel_pm.c:4261:
+ uint16_t plane_blocks, uv_plane_blocks;
total: 0 errors, 0 warnings, 3 checks, 293 lines checked
e8d4aa625cc3 drm/i915/skl+: add NV12 in skl_format_to_fourcc
f995dc9b92e0 drm/i915/skl+: support verification of DDB HW state for NV12
a41cb6ea7434 drm/i915/skl+: NV12 related changes for WM
c1d175ff311e drm/i915/skl+: pass skl_wm_level struct to wm compute func
63822fee142a drm/i915/skl+: make sure higher latency level has higher wm value
59a9d6928dbf drm/i915/skl+: nv12 workaround disable WM level 1-7
-:32: CHECK: Unnecessary parentheses around 'level >= 1'
#32: FILE: drivers/gpu/drm/i915/intel_pm.c:4663:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
-:33: CHECK: Alignment should match open parenthesis
#33: FILE: drivers/gpu/drm/i915/intel_pm.c:4664:
+ if (wp->is_planar && (level >= 1) &&
+ (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
1b76997e221e drm/i915/skl: split skl_compute_ddb function
-:111: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#111: FILE: drivers/gpu/drm/i915/intel_pm.c:5140:
+ uint32_t realloc_pipes = pipes_modified(state);
-:130: CHECK: spaces preferred around that '*' (ctx:ExV)
#130: FILE: drivers/gpu/drm/i915/intel_pm.c:5159:
+ *changed = true;
^
total: 0 errors, 0 warnings, 2 checks, 194 lines checked
03a7f4c2c145 drm/i915: Set scaler mode for NV12
-:55: CHECK: Prefer using the BIT macro
#55: FILE: drivers/gpu/drm/i915/i915_reg.h:6735:
+#define PS_SCALER_MODE_PLANAR (1 << 29)
total: 0 errors, 0 warnings, 1 checks, 21 lines checked
3a9703128148 drm/i915: Update format_is_yuv() to include NV12
01f0c6f70548 drm/i915: Upscale scaler max scale for NV12
-:146: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#146: FILE: drivers/gpu/drm/i915/intel_display.c:12836:
+ uint32_t pixel_format = 0;
total: 0 errors, 0 warnings, 1 checks, 119 lines checked
f1903a03f713 drm/i915: Add NV12 as supported format for primary plane
-:57: CHECK: Unnecessary parentheses around 'pipe == PIPE_C'
#57: FILE: drivers/gpu/drm/i915/intel_display.c:13259:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
-:58: CHECK: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:13260:
+ if ((INTEL_GEN(dev_priv) == 9 && (pipe == PIPE_C)) &&
+ !IS_GEMINILAKE(dev_priv))
total: 0 errors, 0 warnings, 2 checks, 17 lines checked
ae5ae7ff03c9 drm/i915: Add NV12 as supported format for sprite plane
-:71: CHECK: Alignment should match open parenthesis
#71: FILE: drivers/gpu/drm/i915/intel_sprite.c:1374:
+ if ((INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv) &&
+ (plane != 0 || pipe == PIPE_C)) ||
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
ce89283213c8 drm/i915: Add NV12 support to intel_framebuffer_init
-:61: WARNING: line over 80 characters
#61: FILE: drivers/gpu/drm/i915/intel_display.c:14069:
+
drm_get_format_name(mode_cmd->pixel_format,
-:62: CHECK: Alignment should match open parenthesis
#62: FILE: drivers/gpu/drm/i915/intel_display.c:14070:
+
drm_get_format_name(mode_cmd->pixel_format,
+ &format_name));
total: 0 errors, 1 warnings, 1 checks, 14 lines checked
cbd0c912abc5 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:21: CHECK: Prefer using the BIT macro
#21: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709 (1 << 17)
total: 0 errors, 0 warnings, 1 checks, 20 lines checked
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