From: Mahesh Kumar <mahesh1.ku...@intel.com>

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

v3: Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sha...@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srini...@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 77c268f..b575991 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4656,6 +4656,17 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
                }
        }
 
+       /*
+        * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+        * disable wm level 1-7 on NV12 planes
+        */
+       if (wp->is_planar && (level >= 1) &&
+               (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+                IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+               result->plane_en = false;
+               return 0;
+       }
+
        /* The number of lines are ignored for the level 0 watermark. */
        result->plane_res_b = res_blocks;
        result->plane_res_l = res_lines;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to