Preparing a framebuffer should not require a flush. _post_plane_update()
takes care of flushing when a flip is scheduled, this should be
sufficient for PSR and FBC.
Cc: Paulo Zanoni <paulo.r.zan...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 24ca43424c44..c611855bf05a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12717,12 +12717,10 @@ intel_prepare_plane_fb(struct drm_plane *plane,
struct i915_vma *vma;
vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
- if (!IS_ERR(vma)) {
+ if (!IS_ERR(vma))
to_intel_plane_state(new_state)->vma = vma;
- intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
- } else {
+ else
ret = PTR_ERR(vma);
- }
}
i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
--
2.14.1
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