From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.

Bspec: 7021

v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
  - Update for POR changes. (Daniele Ceraolo Spurio)
  - Add provisional guc engine ids - to be checked and confirmed.
v7:
  - Rebased.
  - Added the new ring masks.
  - Added the new HW ids.
v8:
  - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)

v9: increase MAX_ENGINE_INSTANCE to 3

Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Oscar Mateo <oscar.ma...@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Reviewed-by: Oscar Mateo <oscar.ma...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 +++
 drivers/gpu/drm/i915/i915_gem.h          | 2 +-
 drivers/gpu/drm/i915/i915_reg.h          | 5 ++++-
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 9 ++++++++-
 6 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 82a106b1bdbc..9235a60b49d8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2746,6 +2746,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define BLT_RING       ENGINE_MASK(BCS)
 #define VEBOX_RING     ENGINE_MASK(VECS)
 #define BSD2_RING      ENGINE_MASK(VCS2)
+#define BSD3_RING      ENGINE_MASK(VCS3)
+#define BSD4_RING      ENGINE_MASK(VCS4)
+#define VEBOX2_RING    ENGINE_MASK(VECS2)
 #define ALL_ENGINES    (~0)
 
 #define HAS_ENGINE(dev_priv, id) \
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index e920dab7f1b8..1b61b7f8c2ec 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,6 +54,6 @@
 #define GEM_TRACE(...) do { } while (0)
 #endif
 
-#define I915_NUM_ENGINES 5
+#define I915_NUM_ENGINES 8
 
 #endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1412abcb27d4..784d79cbff80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define BCS_HW         2
 #define VECS_HW                3
 #define VCS2_HW                4
+#define VCS3_HW                6
+#define VCS4_HW                7
+#define VECS2_HW       12
 
 /* Engine class */
 
@@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define OTHER_CLASS            4
 #define MAX_ENGINE_CLASS       4
 
-#define MAX_ENGINE_INSTANCE    1
+#define MAX_ENGINE_INSTANCE    3
 
 /* PCI config space */
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..9352f34e75c4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -489,6 +489,9 @@ void intel_device_info_runtime_init(struct 
intel_device_info *info)
                info->num_scalers[PIPE_C] = 1;
        }
 
+       BUILD_BUG_ON(I915_NUM_ENGINES >
+                    sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
+
        /*
         * Skylake and Broxton currently don't expose the topmost plane as its
         * use is exclusive with the legacy cursor and we only want to expose
diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
b/drivers/gpu/drm/i915/intel_device_info.h
index 71fdfb0451ef..4c6f83b2dd6a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,8 @@ struct sseu_dev_info {
        u8 has_eu_pg:1;
 };
 
+typedef u8 intel_ring_mask_t;
+
 struct intel_device_info {
        u16 device_id;
        u16 gen_mask;
@@ -132,7 +134,7 @@ struct intel_device_info {
        u8 gen;
        u8 gt; /* GT number, 0 if undefined */
        u8 num_rings;
-       u8 ring_mask; /* Rings supported by the HW */
+       intel_ring_mask_t ring_mask; /* Rings supported by the HW */
 
        enum intel_platform platform;
        u32 platform_mask;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h 
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index a9b83bf7e837..307013d039d8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -160,6 +160,9 @@ struct i915_ctx_workarounds {
 
 struct i915_request;
 
+#define I915_MAX_VCS   4
+#define I915_MAX_VECS  2
+
 /*
  * Engine IDs definitions.
  * Keep instances of the same type engine together.
@@ -169,8 +172,12 @@ enum intel_engine_id {
        BCS,
        VCS,
        VCS2,
+       VCS3,
+       VCS4,
 #define _VCS(n) (VCS + (n))
-       VECS
+       VECS,
+       VECS2
+#define _VECS(n) (VECS + (n))
 };
 
 struct i915_priolist {
-- 
2.14.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to