Display manufacturers are turning to higher-resolution displays
to differentiate their products. The increased pixel counts have
required increased bandwidth over the links that drive these displays.
However, advances in physical layer technology have not kept up
with the increases in pixel counts.
These factors have created a need for compression on display links.
The Video Electronics Standards Association(VESA),in liaison with the
MIPI Alliance, has developed an industry standard Display Stream
for interoperable, visually lossless compression over display links.
These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms
and provide basic code for future platforms.
Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was no
regression with these patches.
BA Chrome Team (OTC) do not have EDP panel which supports DSC.
Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in
Dropping the patches to get the review started.
Gaurav K Singh (10):
drm: i915: Defining Compression Capabilities
drm: i915: Get DSC capability from DP sink
drm: i915: Enable/Disable DSC in DP sink
drm: i915: Compute RC & DSC parameters
drm: i915: Define Picture Parameter Set
drm/i915: Populate PPS Secondary Data Pkt for Sink
drm: i915: Define VDSC regs and DSC params
drm: i915: Enable VDSC in Source
drm: i915: Disable VDSC from Source
drm/i915: Encoder enable/disable seq wrt DSC
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.h | 589 ++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 451 ++++++++++++
drivers/gpu/drm/i915/intel_ddi.c | 4 +
drivers/gpu/drm/i915/intel_display.c | 20 +
drivers/gpu/drm/i915/intel_dp.c | 182 +++++
drivers/gpu/drm/i915/intel_drv.h | 64 ++
drivers/gpu/drm/i915/intel_vdsc.c | 1243 ++++++++++++++++++++++++++++++++++
include/drm/drm_dp_helper.h | 3 +
9 files changed, 2557 insertions(+)
create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
Intel-gfx mailing list