Hi Matt,

On Wed, Mar 07, 2018 at 04:28:51PM -0800, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood <matthew.s.atw...@intel.com>
> DP_TRAINING_AUX_RD_INTERVAL with DP 1.3 spec changed bit scheeme from 8
> bits to 7 in DPCD 0x000e. The 8th bit is used to identify extended
> receiver capabilities. For panels that use this new feature wait interval
> would be increased by 512 ms, when spec is max 16 ms. This behavior is
> described in table 2-158 of DP 1.4 spec address 0000eh.
> With the introduction of DP 1.4 spec main link clock recovery was
> standardized to 100 us regardless of TRAINING_AUX_RD_INTERVAL value.
> To avoid breaking panels that are not spec compiant we now warn on
> invalid values.
> V2: commit title/message, masking all 7 bits, warn on out of spec values.
> V3: commit message, make link train clock recovery follow DP 1.4 spec.
> V4: style changes
> V5: typo
> Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com>

Tested-by: Benson Leung <ble...@chromium.org>

V5 passes link training on that same panel from before with 8th bit set in
DPCD 0x000e.

Benson Leung
Staff Software Engineer
Chrome OS Kernel
Google Inc.
Chromium OS Project

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