Chris Wilson <[email protected]> writes: > When reporting the frequency table stored in the punit, report the full > range and not just the user restricted frequency range. In the process > keep the code to set the frequency table and read it the same. > > References: f936ec34dea8 ("drm/i915/skl: Updated the i915_ring_freq_table > debugfs function") > Signed-off-by: Chris Wilson <[email protected]> > Cc: Mika Kuoppala <[email protected]> > --- > v2: Typos.
I only noticed one. Reviewed-by: Mika Kuoppala <[email protected]> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 23 ++++++++++------------- > drivers/gpu/drm/i915/intel_pm.c | 9 ++++----- > 2 files changed, 14 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > index e838c765b251..b7723595ae10 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1796,30 +1796,28 @@ static int i915_ring_freq_table(struct seq_file *m, > void *unused) > { > struct drm_i915_private *dev_priv = node_to_i915(m->private); > struct intel_rps *rps = &dev_priv->gt_pm.rps; > - int ret = 0; > - int gpu_freq, ia_freq; > unsigned int max_gpu_freq, min_gpu_freq; > + int gpu_freq, ia_freq; > + int ret; > > if (!HAS_LLC(dev_priv)) > return -ENODEV; > > - intel_runtime_pm_get(dev_priv); > - > ret = mutex_lock_interruptible(&dev_priv->pcu_lock); > if (ret) > - goto out; > + return ret; > > + min_gpu_freq = rps->min_freq; > + max_gpu_freq = rps->max_freq; > if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { > /* Convert GT frequency to 50 HZ units */ > - min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER; > - max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER; > - } else { > - min_gpu_freq = rps->min_freq_softlimit; > - max_gpu_freq = rps->max_freq_softlimit; > + min_gpu_freq /= GEN9_FREQ_SCALER; > + max_gpu_freq /= GEN9_FREQ_SCALER; > } > > seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring > freq (MHz)\n"); > > + intel_runtime_pm_get(dev_priv); > for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) { > ia_freq = gpu_freq; > sandybridge_pcode_read(dev_priv, > @@ -1833,12 +1831,11 @@ static int i915_ring_freq_table(struct seq_file *m, > void *unused) > ((ia_freq >> 0) & 0xff) * 100, > ((ia_freq >> 8) & 0xff) * 100); > } > + intel_runtime_pm_put(dev_priv); > > mutex_unlock(&dev_priv->pcu_lock); > > -out: > - intel_runtime_pm_put(dev_priv); > - return ret; > + return 0; > } > > static int i915_opregion(struct seq_file *m, void *unused) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index b8da4dcdd584..dd5ddb77b306 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -6918,13 +6918,12 @@ static void gen6_update_ring_freq(struct > drm_i915_private *dev_priv) > /* convert DDR frequency from units of 266.6MHz to bandwidth */ > min_ring_freq = mult_frac(min_ring_freq, 8, 3); > > + min_gpu_freq = rps->min_freq; > + max_gpu_freq = rps->max_freq; > if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { > /* Convert GT frequency to 50 HZ units */ > - min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER; > - max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER; > - } else { > - min_gpu_freq = rps->min_freq; > - max_gpu_freq = rps->max_freq; > + min_gpu_freq /= GEN9_FREQ_SCALER; > + max_gpu_freq /= GEN9_FREQ_SCALER; > } > > /* > -- > 2.16.2 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
