On Thu, 08 Mar 2018, matthew.s.atw...@intel.com wrote: > From: Matt Atwood <matthew.s.atw...@intel.com> > > Previously it was assumed that eDP panels would advertise the lowest link > rate required for their singular mode to function. With the introduction > of more advanced features there are advantages to a panel advertising a > higher rate then it needs for a its given mode. For panels that did, the > driver previously used a higher rate then necessary for that mode. > > Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 10 ---------- > 1 file changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index a2eeede..aa6d77d 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1758,16 +1758,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, > dev_priv->vbt.edp.bpp); > bpp = dev_priv->vbt.edp.bpp; > } > - > - /* > - * Use the maximum clock and number of lanes the eDP panel > - * advertizes being capable of. The panels are generally > - * designed to support only a single clock and lane > - * configuration, and typically these values correspond to the > - * native resolution of the panel. > - */ > - min_lane_count = max_lane_count; > - min_clock = max_clock;
Please see my reply to Manasi's identical patch [1]. If we apply this as-is, it will regress and will be reverted. BR, Jani. [1] http://patchwork.freedesktop.org/patch/msgid/1520579339-14745-1-git-send-email-manasi.d.nav...@intel.com > } > > for (; bpp >= 6*3; bpp -= 2*3) { -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
