On 12/03/18 07:52, Chris Wilson wrote:
Quoting Mika Kuoppala (2018-03-12 14:41:31)
Interrupt identity register we already read from hardware
contains engine class and instance fields. Leverage
these fields to find correct engine to handle the interrupt.
add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-160 (-160)
Function old new delta
gen11_irq_handler 764 604 -160
Total: Before=1506953, After=1506793, chg -0.01%
v2: handle class/instance overflow correctly (Mika)
Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
Cc: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
static void
@@ -2825,12 +2787,28 @@ gen11_gt_irq_handler(struct drm_i915_private * const
i915,
}
for_each_set_bit(bit, &intr_dw, 32) {
- const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
+ const u32 ident = gen11_gt_engine_identity(i915,
+ bank, bit);
+ const u16 iir = ident & GEN11_INTR_ENGINE_MASK;
+ u8 class, instance;
+ struct intel_engine_cs *engine;
if (unlikely(!iir))
continue;
Now if (!ident) or actually just use u32 iir as we can pass it straight
through to cs_irq_handler.
Can't use (!ident) here because bit 31 (iir valid) or the class/instance
bits might be set when the iir is empty (because we had a buffered irq
that we actually already handled).
- gen11_gt_engine_irq_handler(i915, bank, bit, iir);
+ class = GEN11_INTR_ENGINE_CLASS(ident);
+ if (unlikely(class >= MAX_ENGINE_CLASS))
+ continue;
+
+ instance = GEN11_INTR_ENGINE_INSTANCE(ident);
+ if (unlikely(instance >= MAX_ENGINE_INSTANCE))
+ continue;
+
+ engine = i915->engine_class[class][instance];
+ if (unlikely(!engine))
+ continue;
Spurious interrupts be spurious; but we are can enable interrupts on a
per-engine basis, right?
irq enable registers are per-class for gen11.
Daniele
-Chris
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