On Mon, Mar 12, 2018 at 11:50:09AM -0700, Rodrigo Vivi wrote:
> On Mon, Mar 12, 2018 at 11:40:26AM -0700, Pandiyan, Dhinakaran wrote:
> > 
> > 
> > 
> > On Mon, 2018-03-12 at 20:29 +0200, Ville Syrjälä wrote:
> > > On Thu, Mar 08, 2018 at 04:52:18PM -0800, Rodrigo Vivi wrote:
> > > > WA 0884:bxt:all,cnl:*:A - "When FBC is enabled with eDP PSR,
> > > > the CPU host modify writes may not get updated on the Display
> > > > as expected.
> > > > WA: Write 0x00000000 to CUR_SURFLIVE_A with every CPU
> > > > host modify write to trigger PSR exit."
> > > > 
> > > > We can also find on spec other cases where they describe
> > > > bogus writes to cursor registers to force PSR exit with
> > > > HW tracking. And it was confirmed by HW engineers that
> > > > this Wa can be safely applied for any frontbuffer activity.
> > > > 
> > > > So let's use this more and more here instead of forcibly
> > > > disable and re-enable PSR everytime that we have a simple
> > > > reliable flush case.
> > > > 
> > > > Other commits improve the fbcon/fbdev use a lot, but this
> > > > approach is the only when where we can get a fully reliable
> > > > console with no slowness or missed frames and PSR still
> > > > enabled and active.
> > > > 
> > > > v2: - Rebase on drm-tip
> > > >     - (DK) Add a comment to explain that WA
> > > >     tells about writing 0 to CUR_SURFLIVE_A but we write to
> > > >     CUR_SURFLIVE(pipe).
> > > > v3: Wa doesn't work on PSR2.
> > > > 
> > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
> > > > Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/i915_reg.h  |  3 +++
> > > >  drivers/gpu/drm/i915/intel_psr.c | 19 +++++++++++++++++--
> > > >  2 files changed, 20 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index e6a8c0ee7df1..abdc513a9edd 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -6032,6 +6032,9 @@ enum {
> > > >  #define IVB_CURSOR_B_OFFSET 0x71080
> > > >  #define IVB_CURSOR_C_OFFSET 0x72080
> > > >  
> > > > +#define _CUR_SURLIVE           0x700AC
> > > > +#define CUR_SURLIVE(pipe)      _CURSOR2(pipe, _CUR_SURLIVE)
> > > 
> > > There should be a better place for this.
> 
> Oh! sorry... my inbox refreshed after I pushed the button :(
> I tried to keep near the cursor regs. Do you want me to move in a
> follow-up patch? where it would be better?

After _CUR_FBC_CTL_A/CUR_FBC_CTL() seems like the correct place based on
the offset. Also could probably use a g4x+ comment.

-- 
Ville Syrjälä
Intel OTC
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