Fix power well control state by reading real register offset.
Signed-off-by: Zhenyu Wang <[email protected]>
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 838d67d..3bcaad6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3812,7 +3812,7 @@ void intel_init_power_wells(struct drm_device *dev)
if ((well & HSW_PWR_WELL_STATE) == 0) {
I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
- if (wait_for(I915_READ(power_wells[i] &
HSW_PWR_WELL_STATE), 20))
+ if (wait_for((I915_READ(power_wells[i]) &
HSW_PWR_WELL_STATE), 20))
DRM_ERROR("Error enabling power well %lx\n",
power_wells[i]);
}
}
--
1.7.10.4
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