Em Ter, 2018-02-27 às 14:22 -0800, James Ausmus escreveu:
> On Thu, Feb 22, 2018 at 12:55:03AM -0300, Paulo Zanoni wrote:
> > There's a lot of code for the PLL enabling, so let's first only
> > introduce the register definitions in order to make patch reviewing
> > a
> > little easier.
> >
> > v2: Coding style (Jani).
> > v3: Preparation for upstreaming.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 149
> > ++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 149 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 1412abcb27d4..f62335c4a748 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8783,6 +8783,12 @@ enum skl_power_gate {
> > #define PORT_CLK_SEL_NONE (7<<29)
> > #define PORT_CLK_SEL_MASK (7<<29)
> >
> > +/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change.
> > */
> > +#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
> > +#define DDI_CLK_SEL_NONE (0x0 << 28)
> > +#define DDI_CLK_SEL_MG (0x8 << 28)
> > +#define DDI_CLK_SEL_MASK (0xF << 28)
> > +
> > /* Transcoder clock selection */
> > #define _TRANS_CLK_SEL_A 0x46140
> > #define _TRANS_CLK_SEL_B 0x46144
> > @@ -8913,6 +8919,7 @@ enum skl_power_gate {
> > * CNL Clocks
> > */
> > #define DPCLKA_CFGCR0 _MMIO(0x6C200
> > )
> > +#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> > #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)
> > == PORT_F ? 23 : \
> > (port)+10))
> > #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) ==
> > PORT_F ? 21 : \
> > @@ -8929,10 +8936,141 @@ enum skl_power_gate {
> > #define PLL_POWER_STATE (1 << 26)
> > #define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE,
> > DPLL1_ENABLE)
> >
> > +#define _MG_PLL1_ENABLE 0x46030
> > +#define _MG_PLL2_ENABLE 0x46034
> > +#define _MG_PLL3_ENABLE 0x46038
> > +#define _MG_PLL4_ENABLE 0x4603C
> > +/* Bits are the same as DPLL0_ENABLE */
> > +#define MG_PLL_ENABLE(port) _MMIO_PORT((port) - PORT_C,
> > _MG_PLL1_ENABLE, \
> > + _MG_PLL2_ENABLE)
> > +
> > +#define _MG_REFCLKIN_CTL_PORT1 0x16
> > 892C
> > +#define _MG_REFCLKIN_CTL_PORT2 0x16
> > 992C
> > +#define _MG_REFCLKIN_CTL_PORT3 0x16
> > A92C
> > +#define _MG_REFCLKIN_CTL_PORT4 0x16
> > B92C
> > +#define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x)
> > << 8)
> > +#define MG_REFCLKIN_CTL(port) _MMIO_PORT((port) - PORT_C, \
> > + _MG_REFCLKIN_CTL_PORT1, \
> > + _MG_REFCLKIN_CTL_PORT2)
> > +
> > +#define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x169
> > 0D8
> > +#define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x16B
> > 0D8
> > +#define _MG_CLKTOP2_CORECLKCTL1_PORT3 0x16D
> > 0D8
> > +#define _MG_CLKTOP2_CORECLKCTL1_PORT4 0x16F
> > 0D8
> > +#define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x)
> > << 16)
> > +#define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x)
> > << 8)
> > +#define MG_CLKTOP2_CORECLKCTL1(port) _MMIO_PORT((port) - PORT_C, \
> > + _MG_CLKTOP2_CORECL
> > KCTL1_PORT1, \
> > + _MG_CLKTOP2_CORECL
> > KCTL1_PORT2)
>
> BSpec 21736 says this register is unused and pending deletion, but in
> 20845 it also
> says to program this register. Art, can you shed any light here?
>
21736 is for a different platform. If you filter for ICL the page
becomes blank.
> Hmm, on further study, it looks like the MG_CLKTOP_CORECLKCTL1 group
> (21340) names the port instances as MG_CLKTOP2_CORECLKCTL1_PORTx, so
> it
> looks like *that* is the actual register group you want (and the
> register bit definitions match as well),
And it's the one that opens when you click it from the icl clocks page
:).
> but, in that case, the
> addresses are wrong - they need to be: 0x1688D8, 0x1698D8, 0x16A8D8,
> and
> 0x16B8D8, respectively.
You're correct, I got this wrong.
>
> > +
> > +#define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4
> > +#define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4
> > +#define _MG_CLKTOP2_HSCLKCTL_PORT3 0x16A8D4
> > +#define _MG_CLKTOP2_HSCLKCTL_PORT4 0x16B8D4
> > +#define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x)
> > << 16)
> > +#define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) <<
> > 14)
> > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x)
> > << 12)
> > +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x)
> > << 8)
> > +#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \
> > + _MG_CLKTOP2_HSCLKCTL_
> > PORT1, \
> > + _MG_CLKTOP2_HSCLKCTL_
> > PORT2)
> > +
> > +#define _MG_PLL_DIV0_PORT1 0x168A00
> > +#define _MG_PLL_DIV0_PORT2 0x169A00
> > +#define _MG_PLL_DIV0_PORT3 0x16AA00
> > +#define _MG_PLL_DIV0_PORT4 0x16BA00
> > +#define MG_PLL_DIV0_FRACNEN_H (1
> > << 30)
> > +#define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) <<
> > 8)
> > +#define MG_PLL_DIV0_FBDIV_INT(x) ((x) <<
> > 0)
> > +#define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C,
> > _MG_PLL_DIV0_PORT1, \
> > + _MG_PLL_DIV0_PORT2)
> > +
> > +#define _MG_PLL_DIV1_PORT1 0x168A04
> > +#define _MG_PLL_DIV1_PORT2 0x169A04
> > +#define _MG_PLL_DIV1_PORT3 0x16AA04
> > +#define _MG_PLL_DIV1_PORT4 0x16BA04
> > +#define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x
> > ) << 16)
> > +#define MG_PLL_DIV1_DITHER_DIV_1 (0 <<
> > 12)
> > +#define MG_PLL_DIV1_DITHER_DIV_2 (1 <<
> > 12)
> > +#define MG_PLL_DIV1_DITHER_DIV_4 (2 <<
> > 12)
> > +#define MG_PLL_DIV1_DITHER_DIV_8 (3 <<
> > 12)
> > +#define MG_PLL_DIV1_NDIVRATIO(x) ((x) <<
> > 4)
> > +#define MG_PLL_DIV1_FBPREDIV(x) ((x) <<
> > 0)
> > +#define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C,
> > _MG_PLL_DIV1_PORT1, \
> > + _MG_PLL_DIV1_PORT2)
> > +
> > +#define _MG_PLL_LF_PORT1 0x168A08
> > +#define _MG_PLL_LF_PORT2 0x169A08
> > +#define _MG_PLL_LF_PORT3 0x16AA08
> > +#define _MG_PLL_LF_PORT4 0x16BA08
> > +#define MG_PLL_LF_TDCTARGETCNT(x) ((x) <<
> > 24)
> > +#define MG_PLL_LF_AFCCNTSEL_256 (0 << 20)
> > +#define MG_PLL_LF_AFCCNTSEL_512 (1 << 20)
> > +#define MG_PLL_LF_GAINCTRL(x) ((x
> > ) << 16)
> > +#define MG_PLL_LF_INT_COEFF(x) ((x) << 8)
> > +#define MG_PLL_LF_PROP_COEFF(x) ((x) <<
> > 0)
> > +#define MG_PLL_LF(port) _MMIO_PORT((port) - PORT_C,
> > _MG_PLL_LF_PORT1, \
> > + _MG_PLL_LF_PORT2)
> > +
> > +#define _MG_PLL_FRAC_LOCK_PORT1 0x1
> > 68A0C
> > +#define _MG_PLL_FRAC_LOCK_PORT2 0x1
> > 69A0C
> > +#define _MG_PLL_FRAC_LOCK_PORT3 0x1
> > 6AA0C
> > +#define _MG_PLL_FRAC_LOCK_PORT4 0x1
> > 6BA0C
> > +#define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 <<
> > 18)
> > +#define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 <<
> > 16)
> > +#define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) <<
> > 11)
> > +#define MG_PLL_FRAC_LOCK_DCODITHEREN (1
> > << 10)
> > +#define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8)
> > +#define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) <<
> > 0)
> > +#define MG_PLL_FRAC_LOCK(port) _MMIO_PORT((port) - PORT_C, \
> > + _MG_PLL_FRAC_LOCK_PORT1,
> > \
> > + _MG_PLL_FRAC_LOCK_PORT2)
> > +
> > +#define _MG_PLL_SSC_PORT1 0x168A10
> > +#define _MG_PLL_SSC_PORT2 0x169A10
> > +#define _MG_PLL_SSC_PORT3 0x16AA10
> > +#define _MG_PLL_SSC_PORT4 0x16BA10
> > +#define MG_PLL_SSC_EN (1
> > << 28)
> > +#define MG_PLL_SSC_TYPE(x) ((x)
> > << 26)
> > +#define MG_PLL_SSC_STEPLENGTH(x) ((x) <<
> > 16)
> > +#define MG_PLL_SSC_STEPNUM(x) ((x
> > ) << 10)
> > +#define MG_PLL_SSC_FILEN (1 << 9)
>
> ^^^
> This should be MG_PLL_SSC_FLLEN
-ENOGLASSES when I wrote this
>
> > +#define MG_PLL_SSC_STEPSIZE(x) ((x) << 0)
> > +#define MG_PLL_SSC(port) _MMIO_PORT((port) - PORT_C,
> > _MG_PLL_SSC_PORT1, \
> > + _MG_PLL_SSC_PORT2)
> > +
> > +#define _MG_PLL_BIAS_PORT1 0x168A14
> > +#define _MG_PLL_BIAS_PORT2 0x169A14
> > +#define _MG_PLL_BIAS_PORT3 0x16AA14
> > +#define _MG_PLL_BIAS_PORT4 0x16BA14
> > +#define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x)
> > << 30)
> > +#define MG_PLL_BIAS_INIT_DCOAMP(x) ((x)
> > << 24)
> > +#define MG_PLL_BIAS_BIAS_BONUS(x) ((x) <<
> > 16)
> > +#define MG_PLL_BIAS_BIASCAL_EN (1 << 15)
> > +#define MG_PLL_BIAS_CTRIM(x) ((x)
> > << 8)
> > +#define MG_PLL_BIAS_VREF_RDAC(x) ((x) <<
> > 5)
> > +#define MG_PLL_BIAS_IREFTRIM(x) ((x) <<
> > 0)
> > +#define MG_PLL_BIAS(port) _MMIO_PORT((port) - PORT_C,
> > _MG_PLL_BIAS_PORT1, \
> > + _MG_PLL_BIAS_PORT2)
> > +
> > +#define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168
> > A18
> > +#define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169
> > A18
> > +#define _MG_PLL_TDC_COLDST_BIAS_PORT3 0x16A
> > A18
> > +#define _MG_PLL_TDC_COLDST_BIAS_PORT4 0x16B
> > A18
> > +#define MG_PLL_TDC_COLDST_IREFINT_EN (1
> > << 27)
> > +#define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x)
> > << 17)
> > +#define MG_PLL_TDC_COLDST_COLDSTART (1 <<
> > 16)
> > +#define MG_PLL_TDC_TDCCOVCCORR_EN (1 <<
> > 2)
>
> ^^^^
> Should be MG_PLL_TDC_TDCOVCCORR_EN
Right.
Thanks for the review!
>
> > +#define MG_PLL_TDC_TDCSEL(x) ((x)
> > << 0)
> > +#define MG_PLL_TDC_COLDST_BIAS(port) _MMIO_PORT((port) - PORT_C, \
> > + _MG_PLL_TDC_COLDST
> > _BIAS_PORT1, \
> > + _MG_PLL_TDC_COLDST
> > _BIAS_PORT2)
> > +
> > #define _CNL_DPLL0_CFGCR0 0x6C000
> > #define _CNL_DPLL1_CFGCR0 0x6C080
> > #define DPLL_CFGCR0_HDMI_MODE (1 << 30)
> > #define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
> > +#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
> > #define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
> > #define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
> > #define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
> > @@ -8966,8 +9104,19 @@ enum skl_power_gate {
> > #define DPLL_CFGCR1_PDIV_5 (4 << 2)
> > #define DPLL_CFGCR1_PDIV_7 (8 << 2)
> > #define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
> > +#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
> > #define CNL_DPLL_CFGCR1(pll) _MMIO_PLL(pll,
> > _CNL_DPLL0_CFGCR1, _CNL_DPLL1_CFGCR1)
> >
> > +#define _ICL_DPLL0_CFGCR0 0x164000
> > +#define _ICL_DPLL1_CFGCR0 0x164080
> > +#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll,
> > _ICL_DPLL0_CFGCR0, \
> > + _ICL_DPLL1_CFGCR
> > 0)
> > +
> > +#define _ICL_DPLL0_CFGCR1 0x164004
> > +#define _ICL_DPLL1_CFGCR1 0x164084
> > +#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll,
> > _ICL_DPLL0_CFGCR1, \
> > + _ICL_DPLL1_CFGCR
> > 1)
> > +
> > /* BXT display engine PLL */
> > #define BXT_DE_PLL_CTL _MMIO(0x6d000)
> > #define BXT_DE_PLL_RATIO(x) (x) /*
> > {60,65,100} * 19.2MHz */
> > --
> > 2.14.3
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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